[coreboot-gerrit] Change in coreboot[master]: nb/intel/model_2065x: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26718


Change subject: nb/intel/model_2065x: Use postcar stage to tear down CAR
......................................................................

nb/intel/model_2065x: Use postcar stage to tear down CAR

Change-Id: I9a81ee6a9f39ced3d33f1caf9c2da43776012775
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_2065x/Makefile.inc
M src/cpu/intel/model_2065x/cache_as_ram.inc
M src/northbridge/intel/nehalem/Makefile.inc
M src/northbridge/intel/nehalem/ram_calc.c
5 files changed, 11 insertions(+), 127 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/26718/1

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 59bb8d8..4bf5b44 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -20,6 +20,8 @@
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config BOOTBLOCK_CPU_INIT
 	string
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 137d1c9..28d7a5e 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -22,3 +22,4 @@
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
 romstage-y += ../car/romstage.c
+postcar-y += ../model_206ax/teardown_car.S
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index 6cc9958..45568a7 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -169,126 +169,7 @@
 	post_code(0x29)
 	/* Call romstage.c main function. */
 	call	romstage_main
-	/* Save return value from romstage_main. It contains the stack to use
-	 * after cache-as-ram is torn down. It also contains the information
-	 * for setting up MTRRs. */
-	movl	%eax, %esp
-
-	post_code(0x30)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	post_code(0x31)
-
-	/* Disable MTRR. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	andl	$(~MTRR_DEF_TYPE_EN), %eax
-	wrmsr
-
-	post_code(0x32)
-
-	/* Disable the no eviction run state */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	andl    $~2, %eax
-	wrmsr
-
-	invd
-
-	/* Disable the no eviction mode */
-	rdmsr
-	andl    $~1, %eax
-	wrmsr
-
-	post_code(0x33)
-
-	/* Enable cache. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x36)
-
-	/* Disable cache. */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-	post_code(0x38)
-
-	/* Clear all of the variable MTRRs. */
-	popl	%ebx
-	movl	$MTRR_PHYS_BASE(0), %ecx
-	clr	%eax
-	clr	%edx
-
-1:
-	testl	%ebx, %ebx
-	jz	1f
-	wrmsr			/* Write MTRR base. */
-	inc	%ecx
-	wrmsr			/* Write MTRR mask. */
-	inc	%ecx
-	dec	%ebx
-	jmp	1b
-
-1:
-	/* Get number of MTRRs. */
-	popl	%ebx
-	movl	$MTRR_PHYS_BASE(0), %ecx
-2:
-	testl	%ebx, %ebx
-	jz	2f
-
-	/* Low 32 bits of MTRR base. */
-	popl	%eax
-	/* Upper 32 bits of MTRR base. */
-	popl	%edx
-	/* Write MTRR base. */
-	wrmsr
-	inc	%ecx
-	/* Low 32 bits of MTRR mask. */
-	popl	%eax
-	/* Upper 32 bits of MTRR mask. */
-	popl	%edx
-	/* Write MTRR mask. */
-	wrmsr
-	inc	%ecx
-
-	dec	%ebx
-	jmp	2b
-2:
-
-	post_code(0x39)
-
-	/* And enable cache again after setting MTRRs. */
-	movl	%cr0, %eax
-	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
-	movl	%eax, %cr0
-
-	post_code(0x3a)
-
-	/* Enable MTRR. */
-	movl	$MTRR_DEF_TYPE_MSR, %ecx
-	rdmsr
-	orl	$MTRR_DEF_TYPE_EN, %eax
-	wrmsr
-
-	post_code(0x3b)
-
-	/* Invalidate the cache again. */
-	invd
-
-	post_code(0x3c)
-
-__main:
-	post_code(POST_PREPARE_RAMSTAGE)
-	cld			/* Clear direction flag. */
-	call	romstage_after_car
+	/* We don't return here */
 
 .Lhlt:
 	post_code(POST_DEAD_CODE)
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index acb828c..6722621 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -29,4 +29,6 @@
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 37c1ed3..b9f2171 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -37,8 +37,6 @@
 	return (void *) smm_region_start();
 }
 
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -46,7 +44,7 @@
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 
-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
 		die("Unable to initialize postcar frame.\n");
 
 	/* Cache the ROM as WP just below 4GiB. */
@@ -64,8 +62,8 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We don't return here */
+	return NULL;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9a81ee6a9f39ced3d33f1caf9c2da43776012775
Gerrit-Change-Number: 26718
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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