[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26714


Change subject: nb/intel/pineview: Use postcar stage to tear down CAR
......................................................................

nb/intel/pineview: Use postcar stage to tear down CAR

Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
A src/cpu/intel/car/teardown_car.S
M src/cpu/intel/socket_FCBGA559/Makefile.inc
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/Makefile.inc
M src/northbridge/intel/pineview/ram_calc.c
5 files changed, 53 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/26714/1

diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S
new file mode 100644
index 0000000..024fc6b
--- /dev/null
+++ b/src/cpu/intel/car/teardown_car.S
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+.global chipset_teardown_car
+chipset_teardown_car:
+	pop %esp
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRR_DEF_TYPE_MSR, %ecx
+	rdmsr
+	andl	$(~MTRR_DEF_TYPE_EN), %eax
+	wrmsr
+
+	post_code(0x32)
+
+	/* Return to caller. */
+	jmp	*%esp
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index dbf300b..6f5ef5c 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -9,4 +9,5 @@
 subdirs-y += ../speedstep
 
 cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index e8ef9d9..80f566a 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -29,6 +29,8 @@
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select RELOCATABLE_RAMSTAGE
 	select INTEL_GMA_ACPI
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index a4c08c8..d7936c1 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -25,4 +25,6 @@
 romstage-y += raminit.c
 romstage-y += early_init.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 63f3942..d2fa66e 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -105,8 +105,6 @@
 	return (void *) top_of_ram;
 }
 
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -114,7 +112,7 @@
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 
-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
 		die("Unable to initialize postcar frame.\n");
 
 	/* Cache the ROM as WP just below 4GiB. */
@@ -133,8 +131,8 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We don't return here */
+	return NULL;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d
Gerrit-Change-Number: 26714
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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