<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26714">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/pineview: Use postcar stage to tear down CAR<br><br>Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/cpu/intel/car/teardown_car.S<br>M src/cpu/intel/socket_FCBGA559/Makefile.inc<br>M src/northbridge/intel/pineview/Kconfig<br>M src/northbridge/intel/pineview/Makefile.inc<br>M src/northbridge/intel/pineview/ram_calc.c<br>5 files changed, 53 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/26714/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/teardown_car.S b/src/cpu/intel/car/teardown_car.S</span><br><span>new file mode 100644</span><br><span>index 0000000..024fc6b</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/car/teardown_car.S</span><br><span>@@ -0,0 +1,43 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+ pop %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x32)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return to caller. */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%esp</span><br><span>diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc</span><br><span>index dbf300b..6f5ef5c 100644</span><br><span>--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc</span><br><span>@@ -9,4 +9,5 @@</span><br><span> subdirs-y += ../speedstep</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_POSTCAR_STAGE) += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig</span><br><span>index e8ef9d9..80f566a 100644</span><br><span>--- a/src/northbridge/intel/pineview/Kconfig</span><br><span>+++ b/src/northbridge/intel/pineview/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span> select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span> select RELOCATABLE_RAMSTAGE</span><br><span> select INTEL_GMA_ACPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config BOOTBLOCK_NORTHBRIDGE_INIT</span><br><span> string</span><br><span>diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc</span><br><span>index a4c08c8..d7936c1 100644</span><br><span>--- a/src/northbridge/intel/pineview/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/pineview/Makefile.inc</span><br><span>@@ -25,4 +25,6 @@</span><br><span> romstage-y += raminit.c</span><br><span> romstage-y += early_init.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>index 63f3942..d2fa66e 100644</span><br><span>--- a/src/northbridge/intel/pineview/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/pineview/ram_calc.c</span><br><span>@@ -105,8 +105,6 @@</span><br><span> return (void *) top_of_ram;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -114,7 +112,7 @@</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1*KiB))</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -133,8 +131,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26714">change 26714</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26714"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5ce488d92cffabad1c73b60e23ded090b07b0a9d </div>
<div style="display:none"> Gerrit-Change-Number: 26714 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>