[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26715


Change subject: nb/intel/gm45: Use postcar stage to tear down CAR
......................................................................

nb/intel/gm45: Use postcar stage to tear down CAR

Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/socket_BGA956/Makefile.inc
M src/cpu/intel/socket_mPGA478MN/Makefile.inc
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/Makefile.inc
M src/northbridge/intel/gm45/ram_calc.c
5 files changed, 11 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26715/1

diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c..bc2019e 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -10,4 +10,5 @@
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+postcar-y += ../car/teardown_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
index 407861e..ee60187 100644
--- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc
@@ -11,4 +11,5 @@
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+postcar-y += ../car/teardown_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 85902d3..193ec70 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,8 @@
 	select RELOCATABLE_RAMSTAGE
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config CBFS_SIZE
 	hex
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index fdf0012..c12bbf1 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -36,4 +36,6 @@
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 1e434c7..6ddb290 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -116,8 +116,6 @@
 	return (void *) top_of_ram;
 }
 
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -125,7 +123,7 @@
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 
-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
 		die("Unable to initialize postcar frame.\n");
 
 	/* Cache the ROM as WP just below 4GiB. */
@@ -144,8 +142,8 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We don't return here */
+	return NULL;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5
Gerrit-Change-Number: 26715
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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