<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26715">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/gm45: Use postcar stage to tear down CAR<br><br>Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/socket_BGA956/Makefile.inc<br>M src/cpu/intel/socket_mPGA478MN/Makefile.inc<br>M src/northbridge/intel/gm45/Kconfig<br>M src/northbridge/intel/gm45/Makefile.inc<br>M src/northbridge/intel/gm45/ram_calc.c<br>5 files changed, 11 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26715/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>index 22c1a7c..bc2019e 100644</span><br><span>--- a/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_BGA956/Makefile.inc</span><br><span>@@ -10,4 +10,5 @@</span><br><span> </span><br><span> # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.</span><br><span> cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>index 407861e..ee60187 100644</span><br><span>--- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>+++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc</span><br><span>@@ -11,4 +11,5 @@</span><br><span> </span><br><span> # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.</span><br><span> cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../car/teardown_car.S</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig</span><br><span>index 85902d3..193ec70 100644</span><br><span>--- a/src/northbridge/intel/gm45/Kconfig</span><br><span>+++ b/src/northbridge/intel/gm45/Kconfig</span><br><span>@@ -29,6 +29,8 @@</span><br><span>        select RELOCATABLE_RAMSTAGE</span><br><span>  select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span>       select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT</span><br><span style="color: hsl(120, 100%, 40%);">+      select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+  select POSTCAR_CONSOLE</span><br><span> </span><br><span> config CBFS_SIZE</span><br><span>       hex</span><br><span>diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc</span><br><span>index fdf0012..c12bbf1 100644</span><br><span>--- a/src/northbridge/intel/gm45/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/gm45/Makefile.inc</span><br><span>@@ -36,4 +36,6 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>index 1e434c7..6ddb290 100644</span><br><span>--- a/src/northbridge/intel/gm45/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/gm45/ram_calc.c</span><br><span>@@ -116,8 +116,6 @@</span><br><span>         return (void *) top_of_ram;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span>  * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -125,7 +123,7 @@</span><br><span>        struct postcar_frame pcf;</span><br><span>    uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-       if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+    if (postcar_frame_init(&pcf, 1*KiB))</span><br><span>             die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span>  /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -144,8 +142,8 @@</span><br><span>     postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span>       postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">-  * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">-      */</span><br><span style="color: hsl(0, 100%, 40%);">-     return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+        run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+        /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+        return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26715">change 26715</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26715"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5261f73a2d4890a0f005958ddee2716179bbf9b5 </div>
<div style="display:none"> Gerrit-Change-Number: 26715 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>