[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_206ax: Use postcar stage to tear down CAR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed May 30 23:59:55 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26713
Change subject: cpu/intel/model_206ax: Use postcar stage to tear down CAR
......................................................................
cpu/intel/model_206ax: Use postcar stage to tear down CAR
Tested on Lenovo Thinkpad X220. Postcar get's loaded by romstage which
in turn loads the ramstage. On S3 both get loaded from the external
stage cache.
Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_206ax/Makefile.inc
M src/cpu/intel/model_206ax/cache_as_ram.inc
A src/cpu/intel/model_206ax/teardown_car.S
M src/northbridge/intel/sandybridge/Makefile.inc
M src/northbridge/intel/sandybridge/ram_calc.c
6 files changed, 68 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/26713/1
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index b30cfa1..0bcf228 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -23,6 +23,8 @@
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 1e04554..a7ae02c 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -13,9 +13,11 @@
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
romstage-y += ../car/romstage.c
+postcar-y += teardown_car.S
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 92d2663..4b0016e 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -189,126 +189,7 @@
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
- /* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
- movl %eax, %esp
-
- post_code(0x30)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x31)
-
- /* Disable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $(~MTRR_DEF_TYPE_EN), %eax
- wrmsr
-
- post_code(0x32)
-
- /* Disable the no eviction run state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- andl $~2, %eax
- wrmsr
-
- invd
-
- /* Disable the no eviction mode */
- rdmsr
- andl $~1, %eax
- wrmsr
-
- post_code(0x33)
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x36)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x38)
-
- /* Clear all of the variable MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
- clr %eax
- clr %edx
-
-1:
- testl %ebx, %ebx
- jz 1f
- wrmsr /* Write MTRR base. */
- inc %ecx
- wrmsr /* Write MTRR mask. */
- inc %ecx
- dec %ebx
- jmp 1b
-
-1:
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
-2:
- testl %ebx, %ebx
- jz 2f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 2b
-2:
-
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call romstage_after_car
+ /* We don't return here */
.Lhlt:
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/model_206ax/teardown_car.S b/src/cpu/intel/model_206ax/teardown_car.S
new file mode 100644
index 0000000..28f0cff
--- /dev/null
+++ b/src/cpu/intel/model_206ax/teardown_car.S
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+#define NoEvictMod_MSR 0x2e0
+
+.global chipset_teardown_car
+chipset_teardown_car:
+ pop %esp
+
+ post_code(0x30)
+
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ post_code(0x31)
+
+ /* Disable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ andl $(~MTRR_DEF_TYPE_EN), %eax
+ wrmsr
+
+ /* Disable the no eviction run state */
+ movl $NoEvictMod_MSR, %ecx
+ rdmsr
+ andl $~2, %eax
+ wrmsr
+ andl $~1, %eax
+ wrmsr
+
+ post_code(0x32)
+
+ /* Return to caller. */
+ jmp *%esp
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index d08b141..3d8da0c 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -46,4 +46,6 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 43442f1..9e3816f 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -44,8 +44,6 @@
return (void *) smm_region_start();
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
void *setup_stack_and_mtrrs(void)
@@ -53,7 +51,7 @@
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
@@ -77,8 +75,8 @@
* handler as well as using the TSEG region for other purposes. */
postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
+
+ /* We don't return here */
+ return NULL;
}
--
To view, visit https://review.coreboot.org/26713
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547
Gerrit-Change-Number: 26713
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180530/08336000/attachment-0001.html>
More information about the coreboot-gerrit
mailing list