<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26713">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/model_206ax: Use postcar stage to tear down CAR<br><br>Tested on Lenovo Thinkpad X220. Postcar get's loaded by romstage which<br>in turn loads the ramstage. On S3 both get loaded from the external<br>stage cache.<br><br>Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_206ax/Kconfig<br>M src/cpu/intel/model_206ax/Makefile.inc<br>M src/cpu/intel/model_206ax/cache_as_ram.inc<br>A src/cpu/intel/model_206ax/teardown_car.S<br>M src/northbridge/intel/sandybridge/Makefile.inc<br>M src/northbridge/intel/sandybridge/ram_calc.c<br>6 files changed, 68 insertions(+), 127 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/26713/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig</span><br><span>index b30cfa1..0bcf228 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Kconfig</span><br><span>+++ b/src/cpu/intel/model_206ax/Kconfig</span><br><span>@@ -23,6 +23,8 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select CPU_INTEL_COMMON</span><br><span> select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span>diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>index 1e04554..a7ae02c 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>@@ -13,9 +13,11 @@</span><br><span> </span><br><span> romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span> ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span> </span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span> romstage-y += ../car/romstage.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += teardown_car.S</span><br><span>diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span>index 92d2663..4b0016e 100644</span><br><span>--- a/src/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span>+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span>@@ -189,126 +189,7 @@</span><br><span> post_code(0x29)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction run state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction mode */</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear all of the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- clr %eax</span><br><span style="color: hsl(0, 100%, 40%);">- clr %edx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 2f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 2b</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span> </span><br><span> .Lhlt:</span><br><span> post_code(POST_DEAD_CODE)</span><br><span>diff --git a/src/cpu/intel/model_206ax/teardown_car.S b/src/cpu/intel/model_206ax/teardown_car.S</span><br><span>new file mode 100644</span><br><span>index 0000000..28f0cff</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/model_206ax/teardown_car.S</span><br><span>@@ -0,0 +1,56 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+.global chipset_teardown_car</span><br><span style="color: hsl(120, 100%, 40%);">+chipset_teardown_car:</span><br><span style="color: hsl(120, 100%, 40%);">+ pop %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x30)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable cache. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %cr0, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl %eax, %cr0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x31)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable MTRR. */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable the no eviction run state */</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ rdmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~2, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+ andl $~1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x32)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Return to caller. */</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp *%esp</span><br><span>diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>index d08b141..3d8da0c 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/sandybridge/Makefile.inc</span><br><span>@@ -46,4 +46,6 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>index 43442f1..9e3816f 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/ram_calc.c</span><br><span>@@ -44,8 +44,6 @@</span><br><span> return (void *) smm_region_start();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define ROMSTAGE_RAM_STACK_SIZE 0x5000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_stack_and_mtrrs() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span> void *setup_stack_and_mtrrs(void)</span><br><span>@@ -53,7 +51,7 @@</span><br><span> struct postcar_frame pcf;</span><br><span> uintptr_t top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1*KiB))</span><br><span> die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span>@@ -77,8 +75,8 @@</span><br><span> * handler as well as using the TSEG region for other purposes. */</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- return postcar_commit_mtrrs(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26713">change 26713</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0f19bbddbf23cbf29a7846479c854980a5286547 </div>
<div style="display:none"> Gerrit-Change-Number: 26713 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>