[coreboot-gerrit] Change in coreboot[master]: [WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc
Arthur Heymans (Code Review)
gerrit at coreboot.org
Wed May 30 20:28:56 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26708
Change subject: [WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc
......................................................................
[WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc
Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/car/cache_as_ram_ht.inc
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_206ax/Makefile.inc
D src/cpu/intel/model_206ax/cache_as_ram.inc
4 files changed, 14 insertions(+), 320 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26708/1
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 7fc92fc..452f052 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -133,6 +133,10 @@
andl $LAPIC_ICR_BUSY, %ecx
jnz 1b
+#if IS_ENABLED(CONFIG_CPU_CAR_SKIP_HALT_AP)
+ jmp sipi_complete
+#endif
+
post_code(0x24)
movl $1, %eax
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index b30cfa1..6857b54 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -23,15 +23,12 @@
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select SIPI_VECTOR_IN_ROM
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
-config XIP_ROM_SIZE
- hex
- default 0x20000 if USE_NATIVE_RAMINIT
-
config SMM_TSEG_SIZE
hex
default 0x800000
@@ -45,4 +42,12 @@
hex
default 0x400000
+config CPU_HAS_NO_EVICT_MODE
+ bool
+ default y
+
+config CPU_CAR_SKIP_HALT_AP
+ bool
+ default y
+
endif
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 1e04554..3e290c1 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -17,5 +17,5 @@
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
-cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
deleted file mode 100644
index d1678bf..0000000
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-
-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
- * and the space used by the reference code. These 2 values combined should
- * be a power of 2 because the MTRR setup assumes that. */
-#define CACHE_AS_RAM_SIZE \
- (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-
-/* Cache 4GB - MRC_SIZE_KB for MRC */
-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-
-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
-
-#define NoEvictMod_MSR 0x2e0
-
- /* Save the BIST result. */
- movl %eax, %ebp
-
-cache_as_ram:
- post_code(0x20)
-
- /* Send INIT IPI to all excluding ourself. */
- movl $0x000C4500, %eax
- movl $0xFEE00300, %esi
- movl %eax, (%esi)
-
- /* All CPUs need to be in Wait for SIPI state */
-wait_for_sipi:
- movl (%esi), %eax
- bt $12, %eax
- jc wait_for_sipi
-
- post_code(0x21)
- /* Zero out all fixed range and variable range MTRRs. */
- movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) >> 1), %edi
- xorl %eax, %eax
- xorl %edx, %edx
-clear_mtrrs:
- movw (%esi), %bx
- movzx %bx, %ecx
- wrmsr
- add $2, %esi
- dec %edi
- jnz clear_mtrrs
-
- post_code(0x22)
- /* Configure the default memory type to uncacheable. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $(~0x00000cff), %eax
- wrmsr
-
- post_code(0x23)
- /* Set Cache-as-RAM base address. */
- movl $(MTRR_PHYS_BASE(0)), %ecx
- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
- wrmsr
-
- post_code(0x24)
- /* Set Cache-as-RAM mask. */
- movl $(MTRR_PHYS_MASK(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-
- post_code(0x25)
-
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-
- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- invd
- movl %eax, %cr0
-
- /* enable the 'no eviction' mode */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $1, %eax
- andl $~2, %eax
- wrmsr
-
- /* Clear the cache memory region. This will also fill up the cache. */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
- // movl $0x23322332, %eax
- xorl %eax, %eax
- rep stosl
-
- /* enable the 'no eviction run' state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $3, %eax
- wrmsr
-
- post_code(0x26)
- /* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- /* Enable cache for our code in Flash because we do XIP here */
- movl $MTRR_PHYS_BASE(1), %ecx
- xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
- */
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
- orl $MTRR_TYPE_WRPROT, %eax
- wrmsr
-
- movl $MTRR_PHYS_MASK(1), %ecx
- movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- wrmsr
-
- post_code(0x27)
- /* Enable caching for RAM init code to run faster */
- movl $MTRR_PHYS_BASE(2), %ecx
- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRR_PHYS_MASK(2), %ecx
- movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-
- post_code(0x28)
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- movl %eax, %cr0
-
- /* Setup the stack. */
- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
- movl %eax, %esp
-
- /* Restore the BIST result. */
- movl %ebp, %eax
- movl %esp, %ebp
- pushl %eax
-
-before_romstage:
- post_code(0x29)
- /* Call romstage.c main function. */
- call romstage_main
- /* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
- movl %eax, %esp
-
- post_code(0x30)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x31)
-
- /* Disable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $(~MTRR_DEF_TYPE_EN), %eax
- wrmsr
-
- post_code(0x32)
-
- /* Disable the no eviction run state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- andl $~2, %eax
- wrmsr
-
- invd
-
- /* Disable the no eviction mode */
- rdmsr
- andl $~1, %eax
- wrmsr
-
- post_code(0x33)
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x36)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x38)
-
- /* Clear all of the variable MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
- clr %eax
- clr %edx
-
-1:
- testl %ebx, %ebx
- jz 1f
- wrmsr /* Write MTRR base. */
- inc %ecx
- wrmsr /* Write MTRR mask. */
- inc %ecx
- dec %ebx
- jmp 1b
-
-1:
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
-2:
- testl %ebx, %ebx
- jz 2f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 2b
-2:
-
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call romstage_after_car
-
-.Lhlt:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .Lhlt
-
-mtrr_table:
- /* Fixed MTRRs */
- .word 0x250, 0x258, 0x259
- .word 0x268, 0x269, 0x26A
- .word 0x26B, 0x26C, 0x26D
- .word 0x26E, 0x26F
- /* Variable MTRRs */
- .word 0x200, 0x201, 0x202, 0x203
- .word 0x204, 0x205, 0x206, 0x207
- .word 0x208, 0x209, 0x20A, 0x20B
- .word 0x20C, 0x20D, 0x20E, 0x20F
- .word 0x210, 0x211, 0x212, 0x213
-mtrr_table_end:
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f
Gerrit-Change-Number: 26708
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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