<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26708">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]cpu/intel/model_206ax: Use cache_as_ram_ht.inc<br><br>Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/car/cache_as_ram_ht.inc<br>M src/cpu/intel/model_206ax/Kconfig<br>M src/cpu/intel/model_206ax/Makefile.inc<br>D src/cpu/intel/model_206ax/cache_as_ram.inc<br>4 files changed, 14 insertions(+), 320 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26708/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>index 7fc92fc..452f052 100644</span><br><span>--- a/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>+++ b/src/cpu/intel/car/cache_as_ram_ht.inc</span><br><span>@@ -133,6 +133,10 @@</span><br><span> andl $LAPIC_ICR_BUSY, %ecx</span><br><span> jnz 1b</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_CPU_CAR_SKIP_HALT_AP)</span><br><span style="color: hsl(120, 100%, 40%);">+ jmp sipi_complete</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> post_code(0x24)</span><br><span> </span><br><span> movl $1, %eax</span><br><span>diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig</span><br><span>index b30cfa1..6857b54 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Kconfig</span><br><span>+++ b/src/cpu/intel/model_206ax/Kconfig</span><br><span>@@ -23,15 +23,12 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select CPU_INTEL_COMMON</span><br><span> select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+ select SIPI_VECTOR_IN_ROM</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span> default "cpu/intel/model_206ax/bootblock.c"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config XIP_ROM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x20000 if USE_NATIVE_RAMINIT</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config SMM_TSEG_SIZE</span><br><span> hex</span><br><span> default 0x800000</span><br><span>@@ -45,4 +42,12 @@</span><br><span> hex</span><br><span> default 0x400000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_HAS_NO_EVICT_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config CPU_CAR_SKIP_HALT_AP</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default y</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span>diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>index 1e04554..3e290c1 100644</span><br><span>--- a/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_206ax/Makefile.inc</span><br><span>@@ -17,5 +17,5 @@</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc</span><br><span> romstage-y += ../car/romstage.c</span><br><span>diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span>deleted file mode 100644</span><br><span>index d1678bf..0000000</span><br><span>--- a/src/cpu/intel/model_206ax/cache_as_ram.inc</span><br><span>+++ /dev/null</span><br><span>@@ -1,315 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com></span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/post_code.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot</span><br><span style="color: hsl(0, 100%, 40%);">- * and the space used by the reference code. These 2 values combined should</span><br><span style="color: hsl(0, 100%, 40%);">- * be a power of 2 because the MTRR setup assumes that. */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_SIZE \</span><br><span style="color: hsl(0, 100%, 40%);">- (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Cache 4GB - MRC_SIZE_KB for MRC */</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)</span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define NoEvictMod_MSR 0x2e0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-cache_as_ram:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x20)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Send INIT IPI to all excluding ourself. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0x000C4500, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $0xFEE00300, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, (%esi)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* All CPUs need to be in Wait for SIPI state */</span><br><span style="color: hsl(0, 100%, 40%);">-wait_for_sipi:</span><br><span style="color: hsl(0, 100%, 40%);">- movl (%esi), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- bt $12, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- jc wait_for_sipi</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x21)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Zero out all fixed range and variable range MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $mtrr_table, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $((mtrr_table_end - mtrr_table) >> 1), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">-clear_mtrrs:</span><br><span style="color: hsl(0, 100%, 40%);">- movw (%esi), %bx</span><br><span style="color: hsl(0, 100%, 40%);">- movzx %bx, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- add $2, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- dec %edi</span><br><span style="color: hsl(0, 100%, 40%);">- jnz clear_mtrrs</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x22)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Configure the default memory type to uncacheable. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~0x00000cff), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x23)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM base address. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_BASE(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x24)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Cache-as-RAM mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(MTRR_PHYS_MASK(0)), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x25)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the 'no eviction' mode */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the cache memory region. This will also fill up the cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CACHE_AS_RAM_BASE, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esi, %edi</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_AS_RAM_SIZE >> 2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- // movl $0x23322332, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- rep stosl</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* enable the 'no eviction run' state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $3, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x26)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable Cache-as-RAM mode by disabling cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache for our code in Flash because we do XIP here */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * IMPORTANT: The following calculation _must_ be done at runtime. See</span><br><span style="color: hsl(0, 100%, 40%);">- * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $copy_and_run, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_TYPE_WRPROT, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(1), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x27)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable caching for RAM init code to run faster */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- xorl %edx, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_MASK(2), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $CPU_PHYSMASK_HI, %edx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x28)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup the stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Restore the BIST result. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %ebp, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %esp, %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- pushl %eax</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-before_romstage:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x29)</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call romstage.c main function. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction run state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction mode */</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear all of the variable MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- clr %eax</span><br><span style="color: hsl(0, 100%, 40%);">- clr %edx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 2f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 2b</span><br><span style="color: hsl(0, 100%, 40%);">-2:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.Lhlt:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(0, 100%, 40%);">- hlt</span><br><span style="color: hsl(0, 100%, 40%);">- jmp .Lhlt</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table:</span><br><span style="color: hsl(0, 100%, 40%);">- /* Fixed MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x250, 0x258, 0x259</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x268, 0x269, 0x26A</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26B, 0x26C, 0x26D</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x26E, 0x26F</span><br><span style="color: hsl(0, 100%, 40%);">- /* Variable MTRRs */</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x200, 0x201, 0x202, 0x203</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x204, 0x205, 0x206, 0x207</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x208, 0x209, 0x20A, 0x20B</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x20C, 0x20D, 0x20E, 0x20F</span><br><span style="color: hsl(0, 100%, 40%);">- .word 0x210, 0x211, 0x212, 0x213</span><br><span style="color: hsl(0, 100%, 40%);">-mtrr_table_end:</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26708">change 26708</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8f73271721072fb3ea4aaaf0b09141d83cf5ff5f </div>
<div style="display:none"> Gerrit-Change-Number: 26708 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>