[coreboot-gerrit] Change in coreboot[master]: mediatek: refactor to sharing uart and timer code among similar SOCs
Tristan Hsieh (Code Review)
gerrit at coreboot.org
Tue May 29 06:41:51 CEST 2018
Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/26658
Change subject: mediatek: refactor to sharing uart and timer code among similar SOCs
......................................................................
mediatek: refactor to sharing uart and timer code among similar SOCs
This patch moves uart and timer code which can be reused
into a common directory under soc/mediatek.
BUG=none
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied)
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh at mediatek.com>
---
A src/soc/mediatek/common/include/soc/timer.h
A src/soc/mediatek/common/timer.c
R src/soc/mediatek/common/uart.c
M src/soc/mediatek/mt8173/Makefile.inc
D src/soc/mediatek/mt8173/include/soc/timer.h
D src/soc/mediatek/mt8173/timer.c
A src/soc/mediatek/mt8173/timer_prepare.c
7 files changed, 149 insertions(+), 146 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/26658/1
diff --git a/src/soc/mediatek/common/include/soc/timer.h b/src/soc/mediatek/common/include/soc/timer.h
new file mode 100644
index 0000000..91b2b83
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/timer.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#pragma once
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+#define GPT4_MHZ 13
+
+struct mtk_gpt_regs {
+ u32 reserved[16];
+ u32 gpt4_con;
+ u32 gpt4_clk;
+ u32 gpt4_cnt;
+};
+
+check_member(mtk_gpt_regs, gpt4_con, 0x0040);
+check_member(mtk_gpt_regs, gpt4_clk, 0x0044);
+check_member(mtk_gpt_regs, gpt4_cnt, 0x0048);
+
+static struct mtk_gpt_regs * const mtk_gpt = (void *)GPT_BASE;
+
+enum {
+ GPT_CON_EN = 0x01,
+ GPT_CON_CLR = 0x02,
+ GPT_MODE_FREERUN = 0x30,
+ GPT_SYS_CLK = 0x00,
+ GPT_CLK_DIV1 = 0x00,
+};
+
+void timer_prepare(void);
diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c
new file mode 100644
index 0000000..29efd39
--- /dev/null
+++ b/src/soc/mediatek/common/timer.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <compiler.h>
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <thread.h>
+
+#include <soc/addressmap.h>
+#include <soc/timer.h>
+
+__weak void timer_prepare(void) { /* do nothing */ }
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ mono_time_set_usecs(mt, read32(&mtk_gpt->gpt4_cnt) / GPT4_MHZ);
+}
+
+/**
+ * init_timer - initialize timer
+ */
+void init_timer(void)
+{
+ timer_prepare();
+
+ /* Disable GPT4 and clear the counter */
+ clrbits_le32(&mtk_gpt->gpt4_con, GPT_CON_EN);
+ setbits_le32(&mtk_gpt->gpt4_con, GPT_CON_CLR);
+
+ /* Set clock source to system clock and set clock divider to 1 */
+ write32(&mtk_gpt->gpt4_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
+ /* Set operation mode to FREERUN mode and enable GTP4 */
+ write32(&mtk_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);
+}
diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/common/uart.c
similarity index 92%
rename from src/soc/mediatek/mt8173/uart.c
rename to src/soc/mediatek/common/uart.c
index 93625c4..eec68d4 100644
--- a/src/soc/mediatek/mt8173/uart.c
+++ b/src/soc/mediatek/common/uart.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2015 MediaTek Inc.
+ * Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -86,10 +86,10 @@
static void mtk_uart_init(void)
{
/* Use a hardcoded divisor for now. */
- const unsigned uartclk = 26 * MHz;
- const unsigned baudrate = get_uart_baudrate();
+ const unsigned int uartclk = 26 * MHz;
+ const unsigned int baudrate = get_uart_baudrate();
const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */
- unsigned highspeed, quot, divisor, remainder;
+ unsigned int highspeed, quot, divisor, remainder;
if (baudrate <= 115200) {
highspeed = 0;
@@ -124,19 +124,21 @@
/* Enable FIFOs, and clear receive and transmit. */
write8(&uart_ptr->fcr,
UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
- UART8250_FCR_CLEAR_XMIT);
+ UART8250_FCR_CLEAR_XMIT);
}
static void mtk_uart_tx_byte(unsigned char data)
{
- while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
+ ;
write8(&uart_ptr->thr, data);
}
static void mtk_uart_tx_flush(void)
{
- while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+ while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
+ ;
}
static unsigned char mtk_uart_rx_byte(void)
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index fecd7f1..8709f65 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -20,10 +20,11 @@
bootblock-y += i2c.c
bootblock-y += pll.c
bootblock-y += spi.c
-bootblock-y += timer.c
+bootblock-y += ../common/timer.c
+bootblock-y += timer_prepare.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
-bootblock-$(CONFIG_DRIVERS_UART) += uart.c
+bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
@@ -35,9 +36,10 @@
verstage-y += i2c.c
verstage-y += spi.c
-verstage-$(CONFIG_DRIVERS_UART) += uart.c
+verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
-verstage-y += timer.c
+verstage-y += ../common/timer.c
+verstage-y += timer_prepare.c
verstage-y += wdt.c
verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
verstage-y += gpio.c
@@ -46,9 +48,10 @@
romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
romstage-y += pll.c
-romstage-y += timer.c
+romstage-y += ../common/timer.c
+romstage-y += timer_prepare.c
-romstage-$(CONFIG_DRIVERS_UART) += uart.c
+romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += cbmem.c
romstage-y += spi.c
romstage-y += gpio.c
@@ -64,8 +67,9 @@
ramstage-y += spi.c
ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
ramstage-y += soc.c mtcmos.c
-ramstage-y += timer.c
-ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += ../common/timer.c
+ramstage-y += timer_prepare.c
+ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
ramstage-y += pmic_wrap.c mt6391.c i2c.c
ramstage-y += mt6311.c
ramstage-y += da9212.c
@@ -90,5 +94,6 @@
./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
endif
diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h
deleted file mode 100644
index ac2f00f..0000000
--- a/src/soc/mediatek/mt8173/include/soc/timer.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_MEDIATEK_MT8173_TIMER_H__
-#define __SOC_MEDIATEK_MT8173_TIMER_H__
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-struct mt8173_gpt_regs {
- u32 irqen;
- u32 irqsta;
- u32 irqack;
- u32 reserved0;
- u32 gpt1_con;
- u32 gpt1_clk;
- u32 gpt1_cnt;
- u32 gpt1_compare;
- u32 gpt2_con;
- u32 gpt2_clk;
- u32 gpt2_cnt;
- u32 gpt2_compare;
- u32 gpt3_con;
- u32 gpt3_clk;
- u32 gpt3_cnt;
- u32 gpt3_compare;
- u32 gpt4_con;
- u32 gpt4_clk;
- u32 gpt4_cnt;
- u32 gpt4_compare;
- u32 gpt5_con;
- u32 gpt5_clk;
- u32 gpt5_cnt;
- u32 gpt5_compare;
- u32 gpt6_con;
- u32 gpt6_clk;
- u32 gpt6_cntl;
- u32 gpt6_comparel;
- u32 reserved1[2];
- u32 gpt6_cnth;
- u32 gpt6_compareh;
- u32 apxgpt_irqmask;
- u32 apxgpt_irqmask1;
-};
-
-static struct mt8173_gpt_regs * const mt8173_gpt = (void *)GPT_BASE;
-
-enum {
- GPT_CON_EN = 0x01,
- GPT_CON_CLR = 0x02,
- GPT_MODE_ONE_SHOT = 0x00,
- GPT_MODE_REPEAT = 0x10,
- GPT_MODE_KEEP_GO = 0x20,
- GPT_MODE_FREERUN = 0x30,
- GPT_SYS_CLK = 0x00,
- GPT_SYS_RTC = 0x01,
-};
-
-#endif /* __SOC_MEDIATEK_MT8173_TIMER_H__ */
diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c
deleted file mode 100644
index b8d8a64..0000000
--- a/src/soc/mediatek/mt8173/timer.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <timer.h>
-#include <delay.h>
-#include <thread.h>
-
-#include <soc/addressmap.h>
-#include <soc/mcucfg.h>
-#include <soc/timer.h>
-
-#define GPT4_MHZ 13
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- mono_time_set_usecs(mt, read32(&mt8173_gpt->gpt4_cnt) / GPT4_MHZ);
-}
-
-/**
- * init_timer - initialize timer
- */
-void init_timer(void)
-{
- /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed
- * with following definition.
- *
- * [10: 8] Clock mode
- * 100: 26Mhz / 4
- * 010: 26Mhz / 2
- * 001: 26Mhz
- * [ 1: 1] Halt-on-debug enable bit
- * [ 0: 0] XGPT enable bit
- */
- write32(&mt8173_mcucfg->xgpt_idx, 0);
- /* Set clock mode to 13Mhz and enable XGPT */
- write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));
-
- /* Disable GPT4 and clear the counter */
- clrbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_EN);
- setbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_CLR);
-
- /* Set clock source to system clock and set clock divider to 1 */
- write32(&mt8173_gpt->gpt4_clk, GPT_SYS_CLK | 0x0);
- /* Set operation mode to FREERUN mode and enable GTP4 */
- write32(&mt8173_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);
-}
diff --git a/src/soc/mediatek/mt8173/timer_prepare.c b/src/soc/mediatek/mt8173/timer_prepare.c
new file mode 100644
index 0000000..300c65a
--- /dev/null
+++ b/src/soc/mediatek/mt8173/timer_prepare.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <soc/mcucfg.h>
+#include <soc/timer.h>
+
+void timer_prepare(void)
+{
+ /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed
+ * with following definition.
+ *
+ * [10: 8] Clock mode
+ * 100: 26Mhz / 4
+ * 010: 26Mhz / 2
+ * 001: 26Mhz
+ * [ 1: 1] Halt-on-debug enable bit
+ * [ 0: 0] XGPT enable bit
+ */
+ write32(&mt8173_mcucfg->xgpt_idx, 0);
+ /* Set clock mode to 13Mhz and enable XGPT */
+ write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Gerrit-Change-Number: 26658
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Hsieh <tristan.shieh at mediatek.com>
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