[coreboot-gerrit] Change in coreboot[master]: src/cpu: Get rid of whitespace before tab

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26648


Change subject: src/cpu: Get rid of whitespace before tab
......................................................................

src/cpu: Get rid of whitespace before tab

Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/allwinner/a10/twi.h
M src/cpu/amd/family_10h-family_15h/defaults.h
M src/cpu/amd/microcode/microcode.c
M src/cpu/x86/smm/smmrelocate.S
4 files changed, 23 insertions(+), 23 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26648/1

diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h
index 1a33419..833b1dc 100644
--- a/src/cpu/allwinner/a10/twi.h
+++ b/src/cpu/allwinner/a10/twi.h
@@ -31,7 +31,7 @@
 
 /* TWI_STAT values */
 enum twi_status {
-	TWI_STAT_BUS_ERROR 	= 0x00,		/**< Bus error */
+	TWI_STAT_BUS_ERROR	= 0x00,		/**< Bus error */
 	TWI_STAT_TX_START	= 0x08,		/**< START sent */
 	TWI_STAT_TX_RSTART	= 0x10,		/**< Repeated START sent */
 	TWI_STAT_TX_AW_ACK	= 0x18,		/**< Sent address+read, ACK */
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
index 88950a3..50b3d07 100644
--- a/src/cpu/amd/family_10h-family_15h/defaults.h
+++ b/src/cpu/amd/family_10h-family_15h/defaults.h
@@ -523,7 +523,7 @@
 	/* Errata 281 Workaround */
 	{ 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
 	 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
-	 	/* [3:0] RspTok = 0001b */
+		/* [3:0] RspTok = 0001b */
 
 	{ 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
 	  0x00000028, 0x000000ff },
@@ -758,7 +758,7 @@
 	  0x0000006d, 0x000000ff },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
 
 	{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
-	  0x0000006d, 0x000000ff }, 	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
+	  0x0000006d, 0x000000ff },	/* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
 
 	/* Link Phy Receiver Loop Filter Registers */
 	{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
@@ -782,28 +782,28 @@
 					  [20:16] RttIndex = 04h */
 
 	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-	  0x00000a2a, 0x000000ff }, 	/* P0RcvRdPtr = 0xa,
-	  				   P0XmtRdPtr = 0x2
-	  				   P1RcvRdPtr = 0xa
-	  				   P1XmtRdPtr = 0x0 */
+	  0x00000a2a, 0x000000ff },	/* P0RcvRdPtr = 0xa,
+					   P0XmtRdPtr = 0x2
+					   P1RcvRdPtr = 0xa
+					   P1XmtRdPtr = 0x0 */
 
 	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
-	  0x00000a2a, 0x000000ff }, 	/* P0RcvRdPtr = 0xa,
-	  				   P0XmtRdPtr = 0x2
-	  				   P1RcvRdPtr = 0xa
-	  				   P1XmtRdPtr = 0x0 */
+	  0x00000a2a, 0x000000ff },	/* P0RcvRdPtr = 0xa,
+					   P0XmtRdPtr = 0x2
+					   P1RcvRdPtr = 0xa
+					   P1XmtRdPtr = 0x0 */
 
 	{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
-	  0x00000d4d, 0x000000ff }, 	/* P0RcvRdPtr = 0xd,
-	  				   P0XmtRdPtr = 0x4
-	  				   P1RcvRdPtr = 0xd
-	  				   P1XmtRdPtr = 0x0 */
+	  0x00000d4d, 0x000000ff },	/* P0RcvRdPtr = 0xd,
+					   P0XmtRdPtr = 0x4
+					   P1RcvRdPtr = 0xd
+					   P1XmtRdPtr = 0x0 */
 
 	{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL,  HTPHY_LINKTYPE_HT1,
-	  0x00000d4d, 0x000000ff }, 	/* P0RcvRdPtr = 0xd,
-	  				   P0XmtRdPtr = 0x4
-	  				   P1RcvRdPtr = 0xd
-	  				   P1XmtRdPtr = 0x0 */
+	  0x00000d4d, 0x000000ff },	/* P0RcvRdPtr = 0xd,
+					   P0XmtRdPtr = 0x4
+					   P1RcvRdPtr = 0xd
+					   P1XmtRdPtr = 0x0 */
 
 	/* Link Phy Receiver Loop Filter Registers */
 	{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 71ecc01..541d5a8 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -30,9 +30,9 @@
 #define UCODE_SECTION_START_ID		0x00000001
 #define UCODE_MAGIC			0x00414d44
 
-#define F1XH_MPB_MAX_SIZE 	2048
-#define F15H_MPB_MAX_SIZE 	4096
-#define CONT_HDR 		12
+#define F1XH_MPB_MAX_SIZE	2048
+#define F15H_MPB_MAX_SIZE	4096
+#define CONT_HDR		12
 #define SECT_HDR		8
 
 /*
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index ed556db..56e73cd 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -67,7 +67,7 @@
  *
  * Example (with SMM handler living at 0xa0000):
  *
- * LAPICID	SMBASE		SMM Entry 	SAVE STATE
+ * LAPICID	SMBASE		SMM Entry	SAVE STATE
  *    0		0xa0000		0xa8000		0xafd00
  *    1		0x9fc00		0xa7c00		0xaf900
  *    2		0x9f800		0xa7800		0xaf500

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470
Gerrit-Change-Number: 26648
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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