<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26648">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/cpu: Get rid of whitespace before tab<br><br>Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/allwinner/a10/twi.h<br>M src/cpu/amd/family_10h-family_15h/defaults.h<br>M src/cpu/amd/microcode/microcode.c<br>M src/cpu/x86/smm/smmrelocate.S<br>4 files changed, 23 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26648/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/allwinner/a10/twi.h b/src/cpu/allwinner/a10/twi.h</span><br><span>index 1a33419..833b1dc 100644</span><br><span>--- a/src/cpu/allwinner/a10/twi.h</span><br><span>+++ b/src/cpu/allwinner/a10/twi.h</span><br><span>@@ -31,7 +31,7 @@</span><br><span> </span><br><span> /* TWI_STAT values */</span><br><span> enum twi_status {</span><br><span style="color: hsl(0, 100%, 40%);">- TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */</span><br><span style="color: hsl(120, 100%, 40%);">+ TWI_STAT_BUS_ERROR = 0x00, /**< Bus error */</span><br><span> TWI_STAT_TX_START = 0x08, /**< START sent */</span><br><span> TWI_STAT_TX_RSTART = 0x10, /**< Repeated START sent */</span><br><span> TWI_STAT_TX_AW_ACK = 0x18, /**< Sent address+read, ACK */</span><br><span>diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h</span><br><span>index 88950a3..50b3d07 100644</span><br><span>--- a/src/cpu/amd/family_10h-family_15h/defaults.h</span><br><span>+++ b/src/cpu/amd/family_10h-family_15h/defaults.h</span><br><span>@@ -523,7 +523,7 @@</span><br><span> /* Errata 281 Workaround */</span><br><span> { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),</span><br><span> AMD_PTYPE_SVR, 0x00000001, 0x0000000F },</span><br><span style="color: hsl(0, 100%, 40%);">- /* [3:0] RspTok = 0001b */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* [3:0] RspTok = 0001b */</span><br><span> </span><br><span> { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,</span><br><span> 0x00000028, 0x000000ff },</span><br><span>@@ -758,7 +758,7 @@</span><br><span> 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */</span><br><span> </span><br><span> { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */</span><br><span> </span><br><span> /* Link Phy Receiver Loop Filter Registers */</span><br><span> { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,</span><br><span>@@ -782,28 +782,28 @@</span><br><span> [20:16] RttIndex = 04h */</span><br><span> </span><br><span> { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,</span><br><span style="color: hsl(0, 100%, 40%);">- P0XmtRdPtr = 0x2</span><br><span style="color: hsl(0, 100%, 40%);">- P1RcvRdPtr = 0xa</span><br><span style="color: hsl(0, 100%, 40%);">- P1XmtRdPtr = 0x0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,</span><br><span style="color: hsl(120, 100%, 40%);">+ P0XmtRdPtr = 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+ P1RcvRdPtr = 0xa</span><br><span style="color: hsl(120, 100%, 40%);">+ P1XmtRdPtr = 0x0 */</span><br><span> </span><br><span> { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,</span><br><span style="color: hsl(0, 100%, 40%);">- P0XmtRdPtr = 0x2</span><br><span style="color: hsl(0, 100%, 40%);">- P1RcvRdPtr = 0xa</span><br><span style="color: hsl(0, 100%, 40%);">- P1XmtRdPtr = 0x0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,</span><br><span style="color: hsl(120, 100%, 40%);">+ P0XmtRdPtr = 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+ P1RcvRdPtr = 0xa</span><br><span style="color: hsl(120, 100%, 40%);">+ P1XmtRdPtr = 0x0 */</span><br><span> </span><br><span> { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,</span><br><span style="color: hsl(0, 100%, 40%);">- P0XmtRdPtr = 0x4</span><br><span style="color: hsl(0, 100%, 40%);">- P1RcvRdPtr = 0xd</span><br><span style="color: hsl(0, 100%, 40%);">- P1XmtRdPtr = 0x0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,</span><br><span style="color: hsl(120, 100%, 40%);">+ P0XmtRdPtr = 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+ P1RcvRdPtr = 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+ P1XmtRdPtr = 0x0 */</span><br><span> </span><br><span> { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,</span><br><span style="color: hsl(0, 100%, 40%);">- P0XmtRdPtr = 0x4</span><br><span style="color: hsl(0, 100%, 40%);">- P1RcvRdPtr = 0xd</span><br><span style="color: hsl(0, 100%, 40%);">- P1XmtRdPtr = 0x0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,</span><br><span style="color: hsl(120, 100%, 40%);">+ P0XmtRdPtr = 0x4</span><br><span style="color: hsl(120, 100%, 40%);">+ P1RcvRdPtr = 0xd</span><br><span style="color: hsl(120, 100%, 40%);">+ P1XmtRdPtr = 0x0 */</span><br><span> </span><br><span> /* Link Phy Receiver Loop Filter Registers */</span><br><span> { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,</span><br><span>diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c</span><br><span>index 71ecc01..541d5a8 100644</span><br><span>--- a/src/cpu/amd/microcode/microcode.c</span><br><span>+++ b/src/cpu/amd/microcode/microcode.c</span><br><span>@@ -30,9 +30,9 @@</span><br><span> #define UCODE_SECTION_START_ID 0x00000001</span><br><span> #define UCODE_MAGIC 0x00414d44</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define F1XH_MPB_MAX_SIZE 2048</span><br><span style="color: hsl(0, 100%, 40%);">-#define F15H_MPB_MAX_SIZE 4096</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONT_HDR 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define F1XH_MPB_MAX_SIZE 2048</span><br><span style="color: hsl(120, 100%, 40%);">+#define F15H_MPB_MAX_SIZE 4096</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONT_HDR 12</span><br><span> #define SECT_HDR 8</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S</span><br><span>index ed556db..56e73cd 100644</span><br><span>--- a/src/cpu/x86/smm/smmrelocate.S</span><br><span>+++ b/src/cpu/x86/smm/smmrelocate.S</span><br><span>@@ -67,7 +67,7 @@</span><br><span> *</span><br><span> * Example (with SMM handler living at 0xa0000):</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * LAPICID SMBASE SMM Entry SAVE STATE</span><br><span style="color: hsl(120, 100%, 40%);">+ * LAPICID SMBASE SMM Entry SAVE STATE</span><br><span> * 0 0xa0000 0xa8000 0xafd00</span><br><span> * 1 0x9fc00 0xa7c00 0xaf900</span><br><span> * 2 0x9f800 0xa7800 0xaf500</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26648">change 26648</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26648"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic501f5f9e8cd79774eb2a8d8902f01853d746470 </div>
<div style="display:none"> Gerrit-Change-Number: 26648 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>