[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apollolake, geminilake}: Make use of FspSkipMpInit for MP ...
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon May 28 14:56:19 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26643
Change subject: soc/intel/{apollolake, geminilake}: Make use of FspSkipMpInit for MP Init
......................................................................
soc/intel/{apollolake, geminilake}: Make use of FspSkipMpInit for MP Init
This patch provides option for mainboard to skip coreboot MP initialization
if requested.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/mainboard/google/octopus/variants/baseboard/devicetree.cb
M src/mainboard/google/octopus/variants/bip/devicetree.cb
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
14 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/26643/1
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index fa86cc4..b969e6a 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -49,6 +49,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb
index 860ca79..aafa4019 100644
--- a/src/mainboard/google/octopus/variants/bip/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb
@@ -49,6 +49,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index da47d42..e3dbed9 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -52,6 +52,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index c1b7067..f89e56d 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -52,6 +52,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index cb297d9..c97893f 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -52,6 +52,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index 16889bb..616f01b 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -49,6 +49,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 9719368..81502fb 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -52,6 +52,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index f7e82a0..8ad5948 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -7,6 +7,9 @@
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 70b28bb..a0c471f 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -55,6 +55,9 @@
# Enable DPTF
register "dptf_enable" = "1"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
# PL1 override: 7.5W setting gives a run-time 6W actual
register "tdp_pl1_override_mw" = "7500"
# Set RAPL PL2 to 15W.
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 6c872b1..682f1a7 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -7,6 +7,9 @@
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 6c872b1..682f1a7 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -7,6 +7,9 @@
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index c1ef76b..74c73ca 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -4,6 +4,9 @@
device lapic 0 on end
end
+ # Skip Multi-Processor Initialization
+ register "FspSkipMpInit" = "1"
+
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index c49f734..9f17145 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -614,7 +614,7 @@
if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
silconfig->MonitorMwaitEnable = 0;
- silconfig->SkipMpInit = 1;
+ silconfig->SkipMpInit = cfg->FspSkipMpInit;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 63ced94..f00924f 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -152,6 +152,12 @@
* (1) Power
* (2) Power & Performance */
enum pnp_settings pnp_settings;
+
+ /*
+ * Skip Multi-Processor Initialization
+ * 0: Initialize(Default), 1: Skip
+ */
+ uint8_t FspSkipMpInit;
};
typedef struct soc_intel_apollolake_config config_t;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Gerrit-Change-Number: 26643
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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