<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26643">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/{apollolake, geminilake}: Make use of FspSkipMpInit for MP Init<br><br>This patch provides option for mainboard to skip coreboot MP initialization<br>if requested.<br><br>Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/mainboard/google/octopus/variants/baseboard/devicetree.cb<br>M src/mainboard/google/octopus/variants/bip/devicetree.cb<br>M src/mainboard/google/reef/variants/baseboard/devicetree.cb<br>M src/mainboard/google/reef/variants/coral/devicetree.cb<br>M src/mainboard/google/reef/variants/pyro/devicetree.cb<br>M src/mainboard/google/reef/variants/sand/devicetree.cb<br>M src/mainboard/google/reef/variants/snappy/devicetree.cb<br>M src/mainboard/intel/apollolake_rvp/devicetree.cb<br>M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb<br>M src/mainboard/intel/leafhill/devicetree.cb<br>M src/mainboard/intel/minnow3/devicetree.cb<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/chip.h<br>14 files changed, 43 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/26643/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>index fa86cc4..b969e6a 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb</span><br><span>@@ -49,6 +49,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Enable Audio Clock and Power gating</span><br><span> register "hdaudio_clk_gate_enable" = "1"</span><br><span> register "hdaudio_pwr_gate_enable" = "1"</span><br><span>diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>index 860ca79..aafa4019 100644</span><br><span>--- a/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb</span><br><span>@@ -49,6 +49,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Enable Audio Clock and Power gating</span><br><span> register "hdaudio_clk_gate_enable" = "1"</span><br><span> register "hdaudio_pwr_gate_enable" = "1"</span><br><span>diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb</span><br><span>index da47d42..e3dbed9 100644</span><br><span>--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb</span><br><span>@@ -52,6 +52,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override 12000 mW: the energy calculation is wrong with the</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span> # be reached when RAPL PL1 is set to 12W.</span><br><span>diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb</span><br><span>index c1b7067..f89e56d 100644</span><br><span>--- a/src/mainboard/google/reef/variants/coral/devicetree.cb</span><br><span>+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb</span><br><span>@@ -52,6 +52,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override 12000 mW: the energy calculation is wrong with the</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span> # be reached when RAPL PL1 is set to 12W.</span><br><span>diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb</span><br><span>index cb297d9..c97893f 100644</span><br><span>--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb</span><br><span>+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb</span><br><span>@@ -52,6 +52,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override 12000 mW: the energy calculation is wrong with the</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span> # be reached when RAPL PL1 is set to 12W.</span><br><span>diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb</span><br><span>index 16889bb..616f01b 100644</span><br><span>--- a/src/mainboard/google/reef/variants/sand/devicetree.cb</span><br><span>+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb</span><br><span>@@ -49,6 +49,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override 12000 mW: the energy calculation is wrong with the</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span> # be reached when RAPL PL1 is set to 12W.</span><br><span>diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb</span><br><span>index 9719368..81502fb 100644</span><br><span>--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb</span><br><span>+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb</span><br><span>@@ -52,6 +52,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override 12000 mW: the energy calculation is wrong with the</span><br><span> # current VR solution. Experiments show that SoC TDP max (6W) can</span><br><span> # be reached when RAPL PL1 is set to 12W.</span><br><span>diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb</span><br><span>index f7e82a0..8ad5948 100644</span><br><span>--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb</span><br><span>@@ -7,6 +7,9 @@</span><br><span> register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span> register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device cpu_cluster 0 on</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>index 70b28bb..a0c471f 100644</span><br><span>--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb</span><br><span>@@ -55,6 +55,9 @@</span><br><span> # Enable DPTF</span><br><span> register "dptf_enable" = "1"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # PL1 override: 7.5W setting gives a run-time 6W actual</span><br><span> register "tdp_pl1_override_mw" = "7500"</span><br><span> # Set RAPL PL2 to 15W.</span><br><span>diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb</span><br><span>index 6c872b1..682f1a7 100644</span><br><span>--- a/src/mainboard/intel/leafhill/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/leafhill/devicetree.cb</span><br><span>@@ -7,6 +7,9 @@</span><br><span> register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span> register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device cpu_cluster 0 on</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb</span><br><span>index 6c872b1..682f1a7 100644</span><br><span>--- a/src/mainboard/intel/minnow3/devicetree.cb</span><br><span>+++ b/src/mainboard/intel/minnow3/devicetree.cb</span><br><span>@@ -7,6 +7,9 @@</span><br><span> register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span> register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> device cpu_cluster 0 on</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>index c1ef76b..74c73ca 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb</span><br><span>@@ -4,6 +4,9 @@</span><br><span> device lapic 0 on end</span><br><span> end</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ # Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ register "FspSkipMpInit" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> register "sci_irq" = "SCIS_IRQ10"</span><br><span> </span><br><span> # Disable unused clkreq of PCIe root ports</span><br><span>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c</span><br><span>index c49f734..9f17145 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.c</span><br><span>+++ b/src/soc/intel/apollolake/chip.c</span><br><span>@@ -614,7 +614,7 @@</span><br><span> if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))</span><br><span> silconfig->MonitorMwaitEnable = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- silconfig->SkipMpInit = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ silconfig->SkipMpInit = cfg->FspSkipMpInit;</span><br><span> </span><br><span> /* Disable setting of EISS bit in FSP. */</span><br><span> silconfig->SpiEiss = 0;</span><br><span>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h</span><br><span>index 63ced94..f00924f 100644</span><br><span>--- a/src/soc/intel/apollolake/chip.h</span><br><span>+++ b/src/soc/intel/apollolake/chip.h</span><br><span>@@ -152,6 +152,12 @@</span><br><span> * (1) Power</span><br><span> * (2) Power & Performance */</span><br><span> enum pnp_settings pnp_settings;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Skip Multi-Processor Initialization</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0: Initialize(Default), 1: Skip</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t FspSkipMpInit;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_apollolake_config config_t;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26643">change 26643</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14 </div>
<div style="display:none"> Gerrit-Change-Number: 26643 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>