[coreboot-gerrit] Change in coreboot[master]: mb/pcengines: Get rid of whitespace before tab

Elyes HAOUAS (Code Review) gerrit at coreboot.org
Mon May 28 13:50:22 CEST 2018


Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26633


Change subject: mb/pcengines: Get rid of whitespace before tab
......................................................................

mb/pcengines: Get rid of whitespace before tab

Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/pcengines/alix1c/devicetree.cb
M src/mainboard/pcengines/alix1c/irq_tables.c
M src/mainboard/pcengines/alix2d/devicetree.cb
M src/mainboard/pcengines/apu1/acpi/gpe.asl
M src/mainboard/pcengines/apu1/acpi/sleep.asl
M src/mainboard/pcengines/apu2/acpi/gpe.asl
M src/mainboard/pcengines/apu2/dsdt.asl
M src/mainboard/pcengines/apu2/mptable.c
8 files changed, 19 insertions(+), 19 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26633/1

diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb
index 20e865a..4000809 100644
--- a/src/mainboard/pcengines/alix1c/devicetree.cb
+++ b/src/mainboard/pcengines/alix1c/devicetree.cb
@@ -1,8 +1,8 @@
 chip northbridge/amd/lx
-  	device domain 0 on
-    		device pci 1.0 on end
+	device domain 0 on
+		device pci 1.0 on end
 		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
+		chip southbridge/amd/cs5536
 			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
 			# SIRQ Mode = Active(Quiet) mode. Save power....
 			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
@@ -25,7 +25,7 @@
 			register "com2_address" = "0x2F8"
 			register "com2_irq" = "3"
 			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-        			device pci f.0 on	# ISA Bridge
+			device pci f.0 on	# ISA Bridge
 				chip superio/winbond/w83627hf
 					device pnp 2e.0 off #  Floppy
 						io 0x60 = 0x3f0
@@ -69,10 +69,10 @@
 			end
 			device pci f.1 on end	# Flash controller
 			device pci f.2 on end	# IDE controller
-        			device pci f.3 on end 	# Audio
-        			device pci f.4 on end	# OHCI
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
 			device pci f.5 on end	# EHCI
-      		end
+		end
 	end
 
 	# APIC cluster is late CPU init.
diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c
index 89ac717..4d85a1f 100644
--- a/src/mainboard/pcengines/alix1c/irq_tables.c
+++ b/src/mainboard/pcengines/alix1c/irq_tables.c
@@ -57,8 +57,8 @@
  * -------------------------------------------------
  * AES          00:01.2 0a      01      A       A
  * 3VPCI        00:0c.0 0a      01      A       A
- * eth0 	00:0d.0 0b      01      A       B
- * mpci 	00:0e.0 0a      01      A       A
+ * eth0	00:0d.0 0b      01      A       B
+ * mpci	00:0e.0 0a      01      A       A
  * usb          00:0f.3 0b      02      B       B
  * usb          00:0f.4 0b      04      D       D
  * usb          00:0f.5 0b      04      D       D
diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb
index f8368ed..5f37140 100644
--- a/src/mainboard/pcengines/alix2d/devicetree.cb
+++ b/src/mainboard/pcengines/alix2d/devicetree.cb
@@ -1,8 +1,8 @@
 chip northbridge/amd/lx
-  	device domain 0 on
-    		device pci 1.0 on end
+	device domain 0 on
+		device pci 1.0 on end
 		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
+		chip southbridge/amd/cs5536
 			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
 			# SIRQ Mode = Active(Quiet) mode. Save power....
 			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
@@ -32,7 +32,7 @@
 			device pci f.2 on end	# IDE controller
 			device pci f.4 on end	# OHCI
 			device pci f.5 on end	# EHCI
-      		end
+		end
 	end
 
 	# APIC cluster is late CPU init.
diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl
index 2f22758..30e6fdc 100644
--- a/src/mainboard/pcengines/apu1/acpi/gpe.asl
+++ b/src/mainboard/pcengines/apu1/acpi/gpe.asl
@@ -72,7 +72,7 @@
 		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
-} 	/* End Scope GPE */
+}	/* End Scope GPE */
 
 /* Contains the GPEs for USB overcurrent */
 #include "usb_oc.asl"
diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl
index d7cf365..ec38a8a 100644
--- a/src/mainboard/pcengines/apu1/acpi/sleep.asl
+++ b/src/mainboard/pcengines/apu1/acpi/sleep.asl
@@ -49,7 +49,7 @@
 
 	/* On older chips, clear PciExpWakeDisEn */
 	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-	*    	Store(0,\_SB.PWDE)
+	*	Store(0,\_SB.PWDE)
 	*}
 	*/
 
diff --git a/src/mainboard/pcengines/apu2/acpi/gpe.asl b/src/mainboard/pcengines/apu2/acpi/gpe.asl
index cd366dc..4a6f6f8 100644
--- a/src/mainboard/pcengines/apu2/acpi/gpe.asl
+++ b/src/mainboard/pcengines/apu2/acpi/gpe.asl
@@ -64,4 +64,4 @@
 		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
 		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
-} 	/* End Scope GPE */
+}	/* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
index d3fb3b1..03bd33e 100644
--- a/src/mainboard/pcengines/apu2/dsdt.asl
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -46,7 +46,7 @@
 
 	/* System Bus */
 	Scope(\_SB) { /* Start \_SB scope */
-	 	/* global utility methods expected within the \_SB scope */
+		/* global utility methods expected within the \_SB scope */
 		#include <arch/x86/acpi/globutil.asl>
 
 		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index 228e281..f62108c 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -40,7 +40,7 @@
 //	0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00,  /* 50 - 57 */
 	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 50 - 57 */
 	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 58 - 5F */
-	0x00,0x00,0x1F 							   /* 60 - 62 */
+	0x00,0x00,0x1F							   /* 60 - 62 */
 };
 u8 intr_data[FCH_INT_TABLE_SIZE] = {
 	0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,  /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
@@ -56,7 +56,7 @@
 //	0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00,  /* 50 - 57 */
 	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 50 - 57 */
 	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 58 - 5F */
-	0x00,0x00,0x1F 							   /* 60 - 62 */
+	0x00,0x00,0x1F							   /* 60 - 62 */
 };
 
 #endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6
Gerrit-Change-Number: 26633
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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