[coreboot-gerrit] Change in coreboot[master]: soc/{amd, intel}: Use postcar_frame_add_romcache()

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/26580


Change subject: soc/{amd,intel}: Use postcar_frame_add_romcache()
......................................................................

soc/{amd,intel}: Use postcar_frame_add_romcache()

Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
6 files changed, 7 insertions(+), 14 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/26580/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 92b1ac2..8fb2c1b 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -125,8 +125,7 @@
 		MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-					MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	/*
 	 * Cache the TSEG region at the top of ram. This region is
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 73b8f7a..96e497a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -233,9 +233,7 @@
 		MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-					MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	/*
 	* Cache the TSEG region at the top of ram. This region is
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index b6cfdba..ae1ba4d 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -142,8 +142,7 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 7073627..105298e 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -172,9 +172,8 @@
 			       MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-				       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	/*
 	 * Cache the TSEG region at the top of ram. This region is
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 7479644..900ec1b 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -80,8 +80,7 @@
 	postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
 
 	/* Cache SPI flash - Write protect not supported */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRTHROUGH);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH);
 
 	run_postcar_phase(&pcf);
 	return NULL;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index a934076..64f9d7d 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -186,8 +186,7 @@
 	}
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Gerrit-Change-Number: 26580
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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