<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26580">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/{amd,intel}: Use postcar_frame_add_romcache()<br><br>Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/soc/amd/stoneyridge/romstage.c<br>M src/soc/intel/apollolake/romstage.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>M src/soc/intel/denverton_ns/romstage.c<br>M src/soc/intel/quark/romstage/fsp2_0.c<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>6 files changed, 7 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/26580/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 92b1ac2..8fb2c1b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -125,8 +125,7 @@</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /*</span><br><span> * Cache the TSEG region at the top of ram. This region is</span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index 73b8f7a..96e497a 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -233,9 +233,7 @@</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /*</span><br><span> * Cache the TSEG region at the top of ram. This region is</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index b6cfdba..ae1ba4d 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -142,8 +142,7 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c</span><br><span>index 7073627..105298e 100644</span><br><span>--- a/src/soc/intel/denverton_ns/romstage.c</span><br><span>+++ b/src/soc/intel/denverton_ns/romstage.c</span><br><span>@@ -172,9 +172,8 @@</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)</span><br><span> /*</span><br><span> * Cache the TSEG region at the top of ram. This region is</span><br><span>diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>index 7479644..900ec1b 100644</span><br><span>--- a/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>+++ b/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>@@ -80,8 +80,7 @@</span><br><span> postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache SPI flash - Write protect not supported */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRTHROUGH);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> return NULL;</span><br><span>diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>index a934076..64f9d7d 100644</span><br><span>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>@@ -186,8 +186,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(0, 100%, 40%);">- MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26580">change 26580</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 </div>
<div style="display:none"> Gerrit-Change-Number: 26580 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>