[coreboot-gerrit] Change in coreboot[master]: soc/{amd, intel}: Use CACHE_ROM_(BASE|SIZE)

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/26575


Change subject: soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
......................................................................

soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)

Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.

Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
6 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/26575/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 0e019f7..92b1ac2 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -125,7 +125,7 @@
 		MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
 					MTRR_TYPE_WRPROT);
 
 	/*
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index bccfc16..73b8f7a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -234,7 +234,7 @@
 
 	/* Cache the memory-mapped boot media. */
 	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
 					MTRR_TYPE_WRPROT);
 
 	/*
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 0459095..b6cfdba 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -142,8 +142,8 @@
 	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
-				CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+			       MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 25d7be0..7073627 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -173,7 +173,7 @@
 
 	/* Cache the memory-mapped boot media. */
 	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
 				       MTRR_TYPE_WRPROT);
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	/*
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 10e44c1..7479644 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -80,8 +80,8 @@
 	postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
 
 	/* Cache SPI flash - Write protect not supported */
-	postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE),
-		CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH);
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+			       MTRR_TYPE_WRTHROUGH);
 
 	run_postcar_phase(&pcf);
 	return NULL;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 760dcc1..a934076 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -186,8 +186,8 @@
 	}
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
-				CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+			       MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Gerrit-Change-Number: 26575
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
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