<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26575">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)<br><br>Boards could choose a high ROM_SIZE that would result in an MTRR config<br>that conflicts with other resources. Thus, always use the filtered<br>CACHE_ROM_SIZE.<br><br>Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/soc/amd/stoneyridge/romstage.c<br>M src/soc/intel/apollolake/romstage.c<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>M src/soc/intel/denverton_ns/romstage.c<br>M src/soc/intel/quark/romstage/fsp2_0.c<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>6 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/26575/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c</span><br><span>index 0e019f7..92b1ac2 100644</span><br><span>--- a/src/soc/amd/stoneyridge/romstage.c</span><br><span>+++ b/src/soc/amd/stoneyridge/romstage.c</span><br><span>@@ -125,7 +125,7 @@</span><br><span> MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c</span><br><span>index bccfc16..73b8f7a 100644</span><br><span>--- a/src/soc/intel/apollolake/romstage.c</span><br><span>+++ b/src/soc/intel/apollolake/romstage.c</span><br><span>@@ -234,7 +234,7 @@</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span> if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index 0459095..b6cfdba 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -142,8 +142,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c</span><br><span>index 25d7be0..7073627 100644</span><br><span>--- a/src/soc/intel/denverton_ns/romstage.c</span><br><span>+++ b/src/soc/intel/denverton_ns/romstage.c</span><br><span>@@ -173,7 +173,7 @@</span><br><span> </span><br><span> /* Cache the memory-mapped boot media. */</span><br><span> if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span> MTRR_TYPE_WRPROT);</span><br><span> #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)</span><br><span> /*</span><br><span>diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>index 10e44c1..7479644 100644</span><br><span>--- a/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>+++ b/src/soc/intel/quark/romstage/fsp2_0.c</span><br><span>@@ -80,8 +80,8 @@</span><br><span> postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span> /* Cache SPI flash - Write protect not supported */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE),</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRTHROUGH);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> return NULL;</span><br><span>diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>index 760dcc1..a934076 100644</span><br><span>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c</span><br><span>@@ -186,8 +186,8 @@</span><br><span> }</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26575">change 26575</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 </div>
<div style="display:none"> Gerrit-Change-Number: 26575 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>