[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

[Nico Huber (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/26567

to look at the new patch set (#2).

Change subject: cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB
......................................................................

cpu/x86/mtrr: Prepare for ROM_SIZE > 16MiB

Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.

Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/include/cpu/x86/mtrr.h
1 file changed, 14 insertions(+), 4 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/26567/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Gerrit-Change-Number: 26567
Gerrit-PatchSet: 2
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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