[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
Nico Huber (Code Review)
gerrit at coreboot.org
Sat May 26 18:15:09 CEST 2018
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/26566
Change subject: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
......................................................................
cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/Kconfig
M src/drivers/intel/fsp1_0/Kconfig
M src/include/cpu/x86/mtrr.h
M src/mainboard/adi/rcc-dff/Kconfig
M src/mainboard/esd/atom15/Kconfig
M src/mainboard/intel/bayleybay_fsp/Kconfig
M src/mainboard/intel/camelbackmountain_fsp/Kconfig
M src/mainboard/intel/minnowmax/Kconfig
M src/mainboard/intel/mohonpeak/Kconfig
M src/mainboard/ocp/monolake/Kconfig
M src/mainboard/ocp/wedge100s/Kconfig
M src/mainboard/siemens/mc_bdx1/Kconfig
M src/mainboard/siemens/mc_tcu3/Kconfig
13 files changed, 20 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26566/1
diff --git a/src/Kconfig b/src/Kconfig
index 99a704d..d6e15f6 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -504,10 +504,6 @@
bool
default n
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x0
-
config USE_WATCHDOG_ON_BOOT
bool
default n
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index 6aa8949..3a9d1a4 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -50,6 +50,8 @@
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
+# Fix vim's syntax highlighting ''
+
config ENABLE_FSP_FAST_BOOT
bool "Enable Fast Boot"
select ENABLE_MRC_CACHE
@@ -103,15 +105,6 @@
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.
-config CACHE_ROM_SIZE_OVERRIDE
- hex "Cache ROM Size"
- default CBFS_SIZE
- help
- This is the size of the cachable area that is passed into the FSP in
- the early initialization. Typically this should be the size of the CBFS
- area, but the size must be a power of 2 whereas the CBFS size does not
- have this limitation.
-
config USE_GENERIC_FSP_CAR_INC
bool
default n
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 0d64be5..ad0e5d6 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -125,6 +125,9 @@
(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
+/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */
+#define FROM_TOP(x) (((1 << 20) - ((x) >> 12)) << 12)
+
/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
* as write-back cacheable to speed up ramstage decompression.
* Note MTRR boundaries, must be power of two.
@@ -135,29 +138,26 @@
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
-/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this
- * resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to
- * use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig.
- */
-#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0)
-# define CACHE_ROM_SIZE CONFIG_CACHE_ROM_SIZE_OVERRIDE
+/* For ROM caching, generally, try to use the next power of 2. */
+#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
+#define OPTIMAL_CACHE_ROM_BASE FROM_TOP(OPTIMAL_CACHE_ROM_SIZE)
+#if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \
+ (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
+# error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement."
+#endif
+
+/* Make sure it doesn't overlap CAR, though. */
+#define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)
+#if CAR_END >= OPTIMAL_CACHE_ROM_BASE
+# define CACHE_ROM_SIZE (_ALIGN_UP_POW2(FROM_TOP(CAR_END)) / 2)
#else
-# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0)
-# define CACHE_ROM_SIZE CONFIG_ROM_SIZE
-# else
-# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
-# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \
- (2 * CONFIG_ROM_SIZE))
-# error "CACHE_ROM_SIZE is not optimal."
-# endif
-# endif
+# define CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE
#endif
-
#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0)
-# error "CACHE_ROM_SIZE is not a power of 2."
+# error "CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."
#endif
-#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
+#define CACHE_ROM_BASE FROM_TOP(CACHE_ROM_SIZE)
#if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \
&& !defined(__ROMCC__))
diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig
index b355934..0673446 100644
--- a/src/mainboard/adi/rcc-dff/Kconfig
+++ b/src/mainboard/adi/rcc-dff/Kconfig
@@ -37,10 +37,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/rangeley/FvFsp.bin"
diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig
index 814177e..8568c51 100644
--- a/src/mainboard/esd/atom15/Kconfig
+++ b/src/mainboard/esd/atom15/Kconfig
@@ -36,10 +36,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index e8318cb..7f74342 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -38,10 +38,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig
index 3d29e2e..295091f 100644
--- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig
+++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig
@@ -23,10 +23,6 @@
int
default 18
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config CBFS_SIZE
hex
default 0x00200000
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index f0c4526..4f7d25d 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -36,10 +36,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 207944e..3a7538f 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -37,10 +37,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/rangeley/FvFsp.bin"
diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig
index 2f253f0..09678c7 100644
--- a/src/mainboard/ocp/monolake/Kconfig
+++ b/src/mainboard/ocp/monolake/Kconfig
@@ -23,10 +23,6 @@
int
default 18
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config CBFS_SIZE
hex
default 0x00200000
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index dfdc552..6a33edb 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -24,10 +24,6 @@
int
default 18
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config CBFS_SIZE
hex
default 0x00200000
diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig
index a24d09d..667a6ee 100644
--- a/src/mainboard/siemens/mc_bdx1/Kconfig
+++ b/src/mainboard/siemens/mc_bdx1/Kconfig
@@ -27,10 +27,6 @@
int
default 18
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x1000000
-
config CBFS_SIZE
hex
default 0x00D00000
diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig
index 6a3b3c4..4be0060 100644
--- a/src/mainboard/siemens/mc_tcu3/Kconfig
+++ b/src/mainboard/siemens/mc_tcu3/Kconfig
@@ -44,10 +44,6 @@
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x1000000
-
config CBFS_SIZE
hex
default 0x00e00000
--
To view, visit https://review.coreboot.org/26566
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Gerrit-Change-Number: 26566
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180526/9192031e/attachment-0001.html>
More information about the coreboot-gerrit
mailing list