<p>Nico Huber has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26566">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE<br><br>As far as I can see this Kconfig option was used wrong ever since it<br>was added. According to the commit message of 107f72e (Re-declare<br>CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary<br>to prevent overlapping with CAR.<br><br>Let's handle the potential overlap in C macros instead and get rid<br>of that option. Currently, it was only used by most FSP1.0 boards,<br>and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).<br><br>Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822<br>Signed-off-by: Nico Huber <nico.h@gmx.de><br>---<br>M src/Kconfig<br>M src/drivers/intel/fsp1_0/Kconfig<br>M src/include/cpu/x86/mtrr.h<br>M src/mainboard/adi/rcc-dff/Kconfig<br>M src/mainboard/esd/atom15/Kconfig<br>M src/mainboard/intel/bayleybay_fsp/Kconfig<br>M src/mainboard/intel/camelbackmountain_fsp/Kconfig<br>M src/mainboard/intel/minnowmax/Kconfig<br>M src/mainboard/intel/mohonpeak/Kconfig<br>M src/mainboard/ocp/monolake/Kconfig<br>M src/mainboard/ocp/wedge100s/Kconfig<br>M src/mainboard/siemens/mc_bdx1/Kconfig<br>M src/mainboard/siemens/mc_tcu3/Kconfig<br>13 files changed, 20 insertions(+), 71 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26566/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/Kconfig b/src/Kconfig</span><br><span>index 99a704d..d6e15f6 100644</span><br><span>--- a/src/Kconfig</span><br><span>+++ b/src/Kconfig</span><br><span>@@ -504,10 +504,6 @@</span><br><span> bool</span><br><span> default n</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config USE_WATCHDOG_ON_BOOT</span><br><span> bool</span><br><span> default n</span><br><span>diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig</span><br><span>index 6aa8949..3a9d1a4 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/Kconfig</span><br><span>+++ b/src/drivers/intel/fsp1_0/Kconfig</span><br><span>@@ -50,6 +50,8 @@</span><br><span> value that is set in the FSP binary. If the FSP needs to be moved,</span><br><span> rebase the FSP with Intel's BCT (tool).</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+# Fix vim's syntax highlighting ''</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config ENABLE_FSP_FAST_BOOT</span><br><span> bool "Enable Fast Boot"</span><br><span> select ENABLE_MRC_CACHE</span><br><span>@@ -103,15 +105,6 @@</span><br><span> the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM</span><br><span> size is 16 MB.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex "Cache ROM Size"</span><br><span style="color: hsl(0, 100%, 40%);">- default CBFS_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">- help</span><br><span style="color: hsl(0, 100%, 40%);">- This is the size of the cachable area that is passed into the FSP in</span><br><span style="color: hsl(0, 100%, 40%);">- the early initialization. Typically this should be the size of the CBFS</span><br><span style="color: hsl(0, 100%, 40%);">- area, but the size must be a power of 2 whereas the CBFS size does not</span><br><span style="color: hsl(0, 100%, 40%);">- have this limitation.</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config USE_GENERIC_FSP_CAR_INC</span><br><span> bool</span><br><span> default n</span><br><span>diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h</span><br><span>index 0d64be5..ad0e5d6 100644</span><br><span>--- a/src/include/cpu/x86/mtrr.h</span><br><span>+++ b/src/include/cpu/x86/mtrr.h</span><br><span>@@ -125,6 +125,9 @@</span><br><span> (x>>6)|(x>>7)|(x>>8)|((1<<18)-1))</span><br><span> #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */</span><br><span style="color: hsl(120, 100%, 40%);">+#define FROM_TOP(x) (((1 << 20) - ((x) >> 12)) << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set</span><br><span> * as write-back cacheable to speed up ramstage decompression.</span><br><span> * Note MTRR boundaries, must be power of two.</span><br><span>@@ -135,29 +138,26 @@</span><br><span> # error "CONFIG_XIP_ROM_SIZE is not a power of 2"</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this</span><br><span style="color: hsl(0, 100%, 40%);">- * resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to</span><br><span style="color: hsl(0, 100%, 40%);">- * use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0)</span><br><span style="color: hsl(0, 100%, 40%);">-# define CACHE_ROM_SIZE CONFIG_CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(120, 100%, 40%);">+/* For ROM caching, generally, try to use the next power of 2. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+#define OPTIMAL_CACHE_ROM_BASE FROM_TOP(OPTIMAL_CACHE_ROM_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+#if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \</span><br><span style="color: hsl(120, 100%, 40%);">+ (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+# error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement."</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Make sure it doesn't overlap CAR, though. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#if CAR_END >= OPTIMAL_CACHE_ROM_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+# define CACHE_ROM_SIZE (_ALIGN_UP_POW2(FROM_TOP(CAR_END)) / 2)</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0)</span><br><span style="color: hsl(0, 100%, 40%);">-# define CACHE_ROM_SIZE CONFIG_ROM_SIZE</span><br><span style="color: hsl(0, 100%, 40%);">-# else</span><br><span style="color: hsl(0, 100%, 40%);">-# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)</span><br><span style="color: hsl(0, 100%, 40%);">-# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \</span><br><span style="color: hsl(0, 100%, 40%);">- (2 * CONFIG_ROM_SIZE))</span><br><span style="color: hsl(0, 100%, 40%);">-# error "CACHE_ROM_SIZE is not optimal."</span><br><span style="color: hsl(0, 100%, 40%);">-# endif</span><br><span style="color: hsl(0, 100%, 40%);">-# endif</span><br><span style="color: hsl(120, 100%, 40%);">+# define CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0)</span><br><span style="color: hsl(0, 100%, 40%);">-# error "CACHE_ROM_SIZE is not a power of 2."</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CACHE_ROM_BASE FROM_TOP(CACHE_ROM_SIZE)</span><br><span> </span><br><span> #if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \</span><br><span> && !defined(__ROMCC__))</span><br><span>diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig</span><br><span>index b355934..0673446 100644</span><br><span>--- a/src/mainboard/adi/rcc-dff/Kconfig</span><br><span>+++ b/src/mainboard/adi/rcc-dff/Kconfig</span><br><span>@@ -37,10 +37,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config FSP_FILE</span><br><span> string</span><br><span> default "../intel/fsp/rangeley/FvFsp.bin"</span><br><span>diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig</span><br><span>index 814177e..8568c51 100644</span><br><span>--- a/src/mainboard/esd/atom15/Kconfig</span><br><span>+++ b/src/mainboard/esd/atom15/Kconfig</span><br><span>@@ -36,10 +36,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config FSP_FILE</span><br><span> string</span><br><span> default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"</span><br><span>diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig</span><br><span>index e8318cb..7f74342 100644</span><br><span>--- a/src/mainboard/intel/bayleybay_fsp/Kconfig</span><br><span>+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig</span><br><span>@@ -38,10 +38,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config FSP_FILE</span><br><span> string</span><br><span> default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP</span><br><span>diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig</span><br><span>index 3d29e2e..295091f 100644</span><br><span>--- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig</span><br><span>+++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig</span><br><span>@@ -23,10 +23,6 @@</span><br><span> int</span><br><span> default 18</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span> default 0x00200000</span><br><span>diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig</span><br><span>index f0c4526..4f7d25d 100644</span><br><span>--- a/src/mainboard/intel/minnowmax/Kconfig</span><br><span>+++ b/src/mainboard/intel/minnowmax/Kconfig</span><br><span>@@ -36,10 +36,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config FSP_FILE</span><br><span> string</span><br><span> default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"</span><br><span>diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig</span><br><span>index 207944e..3a7538f 100644</span><br><span>--- a/src/mainboard/intel/mohonpeak/Kconfig</span><br><span>+++ b/src/mainboard/intel/mohonpeak/Kconfig</span><br><span>@@ -37,10 +37,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config FSP_FILE</span><br><span> string</span><br><span> default "../intel/fsp/rangeley/FvFsp.bin"</span><br><span>diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig</span><br><span>index 2f253f0..09678c7 100644</span><br><span>--- a/src/mainboard/ocp/monolake/Kconfig</span><br><span>+++ b/src/mainboard/ocp/monolake/Kconfig</span><br><span>@@ -23,10 +23,6 @@</span><br><span> int</span><br><span> default 18</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span> default 0x00200000</span><br><span>diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig</span><br><span>index dfdc552..6a33edb 100644</span><br><span>--- a/src/mainboard/ocp/wedge100s/Kconfig</span><br><span>+++ b/src/mainboard/ocp/wedge100s/Kconfig</span><br><span>@@ -24,10 +24,6 @@</span><br><span> int</span><br><span> default 18</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x800000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span> default 0x00200000</span><br><span>diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig</span><br><span>index a24d09d..667a6ee 100644</span><br><span>--- a/src/mainboard/siemens/mc_bdx1/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_bdx1/Kconfig</span><br><span>@@ -27,10 +27,6 @@</span><br><span> int</span><br><span> default 18</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x1000000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span> default 0x00D00000</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig</span><br><span>index 6a3b3c4..4be0060 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/Kconfig</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/Kconfig</span><br><span>@@ -44,10 +44,6 @@</span><br><span> int</span><br><span> default 16</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-config CACHE_ROM_SIZE_OVERRIDE</span><br><span style="color: hsl(0, 100%, 40%);">- hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x1000000</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> config CBFS_SIZE</span><br><span> hex</span><br><span> default 0x00e00000</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26566">change 26566</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 </div>
<div style="display:none"> Gerrit-Change-Number: 26566 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nico Huber <nico.h@gmx.de> </div>