[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
Richard Spiegel (Code Review)
gerrit at coreboot.org
Sat May 26 00:49:55 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26547
Change subject: soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
......................................................................
soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/iomap.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
3 files changed, 57 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/26547/1
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 01171c3..4f3a019 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -51,9 +51,13 @@
#define ACPI_SMI_CTL_PORT 0xb2
#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_STS ACPI_PM_EVT_BLK
+#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 2)
#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define ACPI_GPE0_STS ACPI_GPE0_BLK
+#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 4)
#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 0a23fca..692b94e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -354,6 +354,9 @@
#define FCH_AOAC_STAT0 BIT(6)
#define FCH_AOAC_STAT1 BIT(7)
+#define PM1_LIMIT 16
+#define GPE0_LIMIT 28
+
struct soc_amd_gpio {
uint8_t gpio;
uint8_t function;
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 5a3a442..7fc2d5f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -684,21 +684,24 @@
}
struct soc_amd_sws {
- uint32_t pm1i;
- uint32_t gevent;
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t gpe0_sts;
+ uint32_t gpe0_en;
};
static struct soc_amd_sws sws;
-static void sb_save_sws(uint32_t pm1_status)
+static void sb_save_sws(uint16_t pm1_status)
{
uint32_t reg32;
- sws.pm1i = pm1_status;
- reg32 = inl(ACPI_GPE0_BLK);
- outl(ACPI_GPE0_BLK, reg32);
- reg32 &= inl(ACPI_GPE0_BLK + sizeof(uint32_t));
- sws.gevent = reg32;
+ sws.pm1_sts = pm1_status;
+ sws.pm1_en = inw(ACPI_PM1_EN);
+ reg32 = inl(ACPI_GPE0_STS);
+ outl(ACPI_GPE0_STS, reg32);
+ sws.gpe0_sts = reg32;
+ sws.gpe0_en = inl(ACPI_GPE0_EN);
}
static void sb_clear_pm1_status(void)
@@ -710,19 +713,54 @@
print_pm1_status(pm1_sts);
}
+static int get_index_bit(uint32_t value, int limit)
+{
+ int i;
+ uint32_t t;
+
+ /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */
+ t = ((1 << limit) - 1);
+ if ((value & t) == 0)
+ return -1;
+ t = 1;
+ for (i = 0; i < limit; i++) {
+ if (value & t)
+ break;
+ t <<= 1;
+ }
+ return i;
+}
+
static void set_nvs_sws(void *unused)
{
struct global_nvs_t *gnvs;
+ int index;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs == NULL)
return;
- gnvs->pm1i = sws.pm1i;
- gnvs->gpei = sws.gevent;
+ printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 index ");
+ /* Get the index, but include power button as possible wake */
+ index = get_index_bit((sws.pm1_sts & sws.pm1_en), PM1_LIMIT);
+ if (index < 0) {
+ printk(BIOS_DEBUG, "none");
+ gnvs->pm1i = ~0ULL;
+ } else {
+ printk(BIOS_DEBUG, "%d", index);
+ gnvs->pm1i = index;
+ }
- printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 0x%08x, EVENT 0x%08x into nvs\n",
- sws.pm1i, sws.gevent);
+ printk(BIOS_DEBUG, " EVENT index ");
+ index = get_index_bit((sws.gpe0_sts & sws.gpe0_en), GPE0_LIMIT);
+ if (index < 0) {
+ printk(BIOS_DEBUG, "none\n");
+ gnvs->gpei = ~0ULL;
+ } else {
+ printk(BIOS_DEBUG, "%d\n", index);
+ gnvs->gpei = index;
+ }
+
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Gerrit-Change-Number: 26547
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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