<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26547">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters<br><br>PM1 and GPE0 are being stored directly to NVS, when actually what should<br>be saved is the index of the bit responsible for waking. Fix the procedures<br>and add definitions to the actual IO addresses to be read when recording<br>status and enable registers.<br><br>BUG=b:75996437<br>TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the<br>message indicating which indexes are being save in NVS for _SWS. Try sleep<br>stress test, verify that the index is different from that of power button.<br><br>Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/iomap.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>3 files changed, 57 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/26547/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>index 01171c3..4f3a019 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h</span><br><span>@@ -51,9 +51,13 @@</span><br><span> #define ACPI_SMI_CTL_PORT 0xb2</span><br><span> #define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE</span><br><span> #define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_PM1_STS ACPI_PM_EVT_BLK</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 2)</span><br><span> #define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */</span><br><span> #define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */</span><br><span> #define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_GPE0_STS ACPI_GPE0_BLK</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 4)</span><br><span> #define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */</span><br><span> #define SMB_BASE_ADDR 0xb00</span><br><span> #define PM2_INDEX 0xcd0</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 0a23fca..692b94e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -354,6 +354,9 @@</span><br><span> #define FCH_AOAC_STAT0 BIT(6)</span><br><span> #define FCH_AOAC_STAT1 BIT(7)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define PM1_LIMIT 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE0_LIMIT 28</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_amd_gpio {</span><br><span> uint8_t gpio;</span><br><span> uint8_t function;</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 5a3a442..7fc2d5f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -684,21 +684,24 @@</span><br><span> }</span><br><span> </span><br><span> struct soc_amd_sws {</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t pm1i;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t gevent;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t pm1_en;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t gpe0_en;</span><br><span> };</span><br><span> </span><br><span> static struct soc_amd_sws sws;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb_save_sws(uint32_t pm1_status)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb_save_sws(uint16_t pm1_status)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sws.pm1i = pm1_status;</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(ACPI_GPE0_BLK);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(ACPI_GPE0_BLK, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= inl(ACPI_GPE0_BLK + sizeof(uint32_t));</span><br><span style="color: hsl(0, 100%, 40%);">- sws.gevent = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws.pm1_sts = pm1_status;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws.pm1_en = inw(ACPI_PM1_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = inl(ACPI_GPE0_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ outl(ACPI_GPE0_STS, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+ sws.gpe0_sts = reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ sws.gpe0_en = inl(ACPI_GPE0_EN);</span><br><span> }</span><br><span> </span><br><span> static void sb_clear_pm1_status(void)</span><br><span>@@ -710,19 +713,54 @@</span><br><span> print_pm1_status(pm1_sts);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static int get_index_bit(uint32_t value, int limit)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int i;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t t;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ t = ((1 << limit) - 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((value & t) == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ t = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = 0; i < limit; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value & t)</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ t <<= 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return i;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void set_nvs_sws(void *unused)</span><br><span> {</span><br><span> struct global_nvs_t *gnvs;</span><br><span style="color: hsl(120, 100%, 40%);">+ int index;</span><br><span> </span><br><span> gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);</span><br><span> if (gnvs == NULL)</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- gnvs->pm1i = sws.pm1i;</span><br><span style="color: hsl(0, 100%, 40%);">- gnvs->gpei = sws.gevent;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 index ");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get the index, but include power button as possible wake */</span><br><span style="color: hsl(120, 100%, 40%);">+ index = get_index_bit((sws.pm1_sts & sws.pm1_en), PM1_LIMIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (index < 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "none");</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pm1i = ~0ULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%d", index);</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pm1i = index;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 0x%08x, EVENT 0x%08x into nvs\n",</span><br><span style="color: hsl(0, 100%, 40%);">- sws.pm1i, sws.gevent);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, " EVENT index ");</span><br><span style="color: hsl(120, 100%, 40%);">+ index = get_index_bit((sws.gpe0_sts & sws.gpe0_en), GPE0_LIMIT);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (index < 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "none\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->gpei = ~0ULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%d\n", index);</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->gpei = index;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> }</span><br><span> </span><br><span> BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26547">change 26547</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26547"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 </div>
<div style="display:none"> Gerrit-Change-Number: 26547 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>