[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Fri May 25 13:02:41 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26541
Change subject: soc/intel/skylake: Get rid of device_t
......................................................................
soc/intel/skylake: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/acpi.h
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/smmrelocate.c
M src/soc/intel/skylake/vr_config.c
9 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/26541/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 43487c4..be1200b 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -495,13 +495,13 @@
acpigen_pop_len();
}
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
{
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6;
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info;
int is_s0ix_enable = config->s0ix_enable;
int max_c_state;
@@ -629,7 +629,7 @@
return current;
}
-unsigned long southbridge_write_acpi_tables(device_t device,
+unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@@ -640,7 +640,7 @@
return acpi_align_current(current);
}
-void southbridge_inject_dsdt(device_t device)
+void southbridge_inject_dsdt(struct device *device)
{
global_nvs_t *gnvs;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index bb2ecaa..1e3fdc6 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -39,7 +39,7 @@
fsp_load();
}
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -60,7 +60,7 @@
#endif
};
-static void soc_enable(device_t dev)
+static void soc_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index a4867ea..bc78586 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -50,7 +50,7 @@
fsps_load(romstage_handoff_is_resume());
}
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -75,7 +75,7 @@
#endif
};
-static void soc_enable(device_t dev)
+static void soc_enable(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index d9e90d2..d386d1f 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -119,7 +119,7 @@
unsigned int power_unit;
unsigned int tdp, min_power, max_power, max_time, tdp_pl2;
u8 power_limit_1_val;
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
@@ -241,7 +241,7 @@
static void configure_thermal_target(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@@ -261,7 +261,7 @@
static void configure_isst(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@@ -287,7 +287,7 @@
static void configure_misc(void)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
@@ -419,7 +419,7 @@
}
/* All CPUs including BSP will run the following function. */
-void soc_core_init(device_t cpu)
+void soc_core_init(struct device *cpu)
{
/* Clear out pending MCEs */
/* TODO(adurbin): This should only be done on a cold boot. Also, some
@@ -544,7 +544,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
assert(dev != NULL);
config_t *conf = dev->chip_info;
@@ -558,7 +558,7 @@
}
int soc_fill_vmx_param(struct vmx_param *vmx_param)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
assert(dev != NULL);
config_t *conf = dev->chip_info;
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 25b7484..d75f810 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -39,7 +39,7 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
+static void pch_configure_endpoints(struct device *dev, int epmask_id, uint32_t mask)
{
uint32_t reg32;
@@ -49,7 +49,7 @@
static void disable_sideband_access(void)
{
- device_t dev;
+ struct device *dev;
u8 reg8;
uint32_t mask;
@@ -82,7 +82,7 @@
static void pch_disable_heci(void)
{
- device_t dev = PCH_DEV_P2SB;
+ struct device *dev = PCH_DEV_P2SB;
/*
* if p2sb device 1f.1 is not present or hidden in devicetree
@@ -103,7 +103,7 @@
static void pch_finalize_script(void)
{
- device_t dev;
+ struct device *dev;
uint32_t reg32;
uint8_t *pmcbase;
config_t *config;
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index 6d492ac..c39c066 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -29,8 +29,8 @@
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_mainboard_gnvs(global_nvs_t *gnvs);
-void southbridge_inject_dsdt(device_t device);
-unsigned long southbridge_write_acpi_tables(device_t device,
+void southbridge_inject_dsdt(struct device *device);
+unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
unsigned long northbridge_write_acpi_tables(struct device *,
unsigned long current, struct acpi_rsdp *);
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index 50119a5..146fcda 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -296,7 +296,7 @@
{
const config_t *config = dev->chip_info;
uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
- device_t irq_dev;
+ struct device *irq_dev;
pch_interrupt_routing[0] = config->pirqa_routing;
pch_interrupt_routing[1] = config->pirqb_routing;
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index b477b11..6a8e64b 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -180,7 +180,7 @@
write_smrr(relo_params);
}
-static void fill_in_relocation_params(device_t dev,
+static void fill_in_relocation_params(struct device *dev,
struct smm_relocation_params *params)
{
void *handler_base;
@@ -265,7 +265,7 @@
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
- device_t dev = SA_DEV_ROOT;
+ struct device *dev = SA_DEV_ROOT;
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 0659d04..57affe5 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -160,7 +160,7 @@
},
};
-static uint16_t get_dev_id(device_t dev)
+static uint16_t get_dev_id(struct device *dev)
{
return pci_read_config16(dev, PCI_DEVICE_ID);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7
Gerrit-Change-Number: 26541
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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