[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Add careena variant
Martin Roth (Code Review)
gerrit at coreboot.org
Fri May 25 01:14:16 CEST 2018
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26524
Change subject: mainboard/google/kahlee: Add careena variant
......................................................................
mainboard/google/kahlee: Add careena variant
Add Careena variant, based on the grunt board.
BUG=b:80106042
TEST=Build Careena
Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/kahlee/Kconfig.name
A src/mainboard/google/kahlee/variants/careena/Makefile.inc
A src/mainboard/google/kahlee/variants/careena/chromeos.fmd
A src/mainboard/google/kahlee/variants/careena/devicetree.cb
A src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl
A src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl
A src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl
A src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl
A src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl
A src/mainboard/google/kahlee/variants/careena/include/variant/ec.h
A src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h
A src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h
A src/mainboard/google/kahlee/variants/careena/mainboard.c
A src/mainboard/google/kahlee/variants/careena/romstage.c
15 files changed, 443 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/26524/1
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 24881b5..8551698 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -18,8 +18,8 @@
select SOC_AMD_STONEYRIDGE_FT4
select ALWAYS_LOAD_OPROM
select ALWAYS_RUN_OPROM
- select BOARD_ROMSIZE_KB_16384 if BOARD_GOOGLE_GRUNT
select BOARD_ROMSIZE_KB_8192 if BOARD_GOOGLE_KAHLEE
+ select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_GENERIC
select DRIVERS_PS2_KEYBOARD
select EC_GOOGLE_CHROMEEC
@@ -36,7 +36,7 @@
select SOC_AMD_PSP_SELECTABLE_SMU_FW
select SOC_AMD_SMU_FANLESS
select HAVE_ACPI_RESUME
- select DRIVERS_GENERIC_BH720 if BOARD_GOOGLE_GRUNT
+ select DRIVERS_GENERIC_BH720 if !BOARD_GOOGLE_KAHLEE
if BOARD_GOOGLE_BASEBOARD_KAHLEE
@@ -46,11 +46,13 @@
config VARIANT_DIR
string
+ default "careena" if BOARD_GOOGLE_CAREENA
default "grunt" if BOARD_GOOGLE_GRUNT
default "kahlee" if BOARD_GOOGLE_KAHLEE
config MAINBOARD_PART_NUMBER
string
+ default "Careena" if BOARD_GOOGLE_CAREENA
default "Grunt" if BOARD_GOOGLE_GRUNT
default "Kahlee" if BOARD_GOOGLE_KAHLEE
@@ -97,6 +99,7 @@
config GBB_HWID
string
depends on CHROMEOS
+ default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA
default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT
default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE
diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name
index 9648057..98f9be1 100644
--- a/src/mainboard/google/kahlee/Kconfig.name
+++ b/src/mainboard/google/kahlee/Kconfig.name
@@ -1,5 +1,8 @@
comment "Kahlee"
+config BOARD_GOOGLE_CAREENA
+ bool "-> Careena"
+ select BOARD_GOOGLE_BASEBOARD_KAHLEE
config BOARD_GOOGLE_GRUNT
bool "-> Grunt"
select BOARD_GOOGLE_BASEBOARD_KAHLEE
diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc
new file mode 100644
index 0000000..319ab4e
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc
@@ -0,0 +1,38 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
+
+
+LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/spd/$(f).spd.hex)
+
+SPD_SOURCES = hynix-H5AN8G6NAFR-UH # 0b0000
+SPD_SOURCES += hynix-H5ANAG6NAMR-UH # 0b0001
+SPD_SOURCES += micron-MT40A512M16JY-083E:B # 0b0010
+SPD_SOURCES += micron-MT40A1G16KNR-075:E # 0b0011
+SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0100
+SPD_SOURCES += samsung-K4AAG165WB-MCRC # 0b0101
+SPD_SOURCES += empty # 0b0110
+SPD_SOURCES += empty # 0b0111
+SPD_SOURCES += empty # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += empty # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += empty # 0b1100
+SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
diff --git a/src/mainboard/google/kahlee/variants/careena/chromeos.fmd b/src/mainboard/google/kahlee/variants/careena/chromeos.fmd
new file mode 100644
index 0000000..336aced
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/chromeos.fmd
@@ -0,0 +1,41 @@
+FLASH at 0xFF000000 0x1000000 {
+ SI_BIOS at 0x0 0x1000000 {
+ UNIFIED_MRC_CACHE at 0x0 0x21000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ RW_VAR_MRC_CACHE at 0x20000 0x1000
+ }
+ RW_SECTION_A at 0x21000 0x21E000 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x20DFC0
+ RW_FWID_A at 0x21DFC0 0x40
+ }
+ RW_SECTION_B at 0x23F000 0x21E000 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x20DFC0
+ RW_FWID_B at 0x21DFC0 0x40
+ }
+ RW_ELOG at 0x45D000 0x4000
+
+ RW_SHARED at 0x461000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x465000 0x2000
+ RW_NVRAM at 0x467000 0x5000
+ RW_UNUSED at 0x46C000 0x14000
+ RW_LEGACY at 0x480000 0x780000
+
+ WP_RO at 0xC00000 0x400000 {
+ RO_VPD at 0x0 0x4000
+ RO_UNUSED at 0x4000 0x17B000
+ RO_SECTION at 0x17F000 0x281000 {
+ FMAP at 0x0 0x800
+ RO_FRID at 0x800 0x40
+ RO_FRID_PAD at 0x840 0x7c0
+ GBB at 0x1000 0x70000
+ COREBOOT(CBFS)@0x71000 0x210000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb
new file mode 100644
index 0000000..3863100
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb
@@ -0,0 +1,164 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip soc/amd/stoneyridge
+ register "spd_addr_lookup" = "
+ {
+ { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
+ }"
+ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
+ register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
+ register "uma_size" = "32 * MiB"
+
+ # Enable I2C0 for audio, USB3 hub at 400kHz
+ register "i2c[0]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 95,
+ .fall_time_ns = 3,
+ }"
+
+ # Enable I2C1 for H1 at 400kHz
+ register "i2c[1]" = "{
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 84,
+ .fall_time_ns = 4,
+ }"
+
+ # Enable I2C2 for trackpad, pen at 400kHz
+ register "i2c[2]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 117,
+ .fall_time_ns = 113,
+ }"
+
+ # Enable I2C3 for touchscreen at 400kHz
+ register "i2c[3]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 82,
+ .fall_time_ns = 67,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 10 on end
+ end
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end #
+ device pci 2.2 on end #
+ device pci 2.3 on end #
+ device pci 2.4 on
+ chip drivers/generic/bayhub
+ register "power_saving" = "1"
+ device pci 00.0 on end
+ end
+ end #
+ device pci 2.5 on end #
+ device pci 8.0 on end # PSP
+ device pci 9.0 on end # PCIe Host Bridge
+ device pci 9.2 on end # HDA
+ device pci 10.0 on end # xHCI
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # EHCI
+ device pci 14.0 on # SMbus
+ end # SMbus
+ device pci 14.3 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC
+ device pci 14.7 on end # SD
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ end #domain
+ device mmio 0xfedc2000 on
+ chip drivers/generic/adau7002
+ device generic 0.0 on end
+ end
+ chip drivers/i2c/da7219
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)"
+ register "btn_cfg" = "50"
+ register "mic_det_thr" = "500"
+ register "jack_ins_deb" = "20"
+ register "jack_det_rate" = ""32ms_64ms""
+ register "jack_rem_deb" = "1"
+ register "a_d_btn_thr" = "0xa"
+ register "d_b_btn_thr" = "0x16"
+ register "b_c_btn_thr" = "0x21"
+ register "c_mic_btn_thr" = "0x3e"
+ register "btn_avg" = "4"
+ register "adc_1bit_rpt" = "1"
+ register "micbias_lvl" = "2600"
+ register "mic_amp_in_sel" = ""diff""
+ register "mclk_name" = ""oscout1""
+ device i2c 1a on end
+ end
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)"
+ register "sdmode_delay" = "5"
+ device generic 0.1 on end
+ end
+ end
+ device mmio 0xfedc3000 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "desc" = ""Cr50 TPM""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+ device i2c 50 on end
+ end
+ end
+ device mmio 0xfedc4000 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)"
+ register "wake" = "7"
+ device i2c 15 on end
+ end
+ end
+ device mmio 0xfedc5000 on
+ chip drivers/i2c/generic
+ register "hid" = ""RAYD0001""
+ register "desc" = ""Raydium Touchscreen""
+ register "probed" = "1"
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 39 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "probed" = "1"
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ end
+end #chip soc/amd/stoneyridge
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl
new file mode 100644
index 0000000..0a08774
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/gpe.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/gpe.asl>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000..4f91d72
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/mainboard.asl>
+#include <baseboard/acpi/audio.asl>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl
new file mode 100644
index 0000000..233494f
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/routing.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/routing.asl>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl
new file mode 100644
index 0000000..c5a1557
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/sleep.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/sleep.asl>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000..77137bb
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/acpi/thermal.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/thermal.asl>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h b/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h
new file mode 100644
index 0000000..96388ae
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/ec.h
@@ -0,0 +1,4 @@
+#include <baseboard/ec.h>
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h
new file mode 100644
index 0000000..5a6b540
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/gpio.h
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h
new file mode 100644
index 0000000..2c983bb
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/*
+ * Stoney Ridge Thermal Requirements 12 (6W)
+ * TDP (W) 6
+ * T die,max (°C) 95
+ * T ctl,max 85
+ * T die,lmt (default) 90
+ * T ctl,lmt (default) 80
+ */
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 94
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 85
+
+#endif
diff --git a/src/mainboard/google/kahlee/variants/careena/mainboard.c b/src/mainboard/google/kahlee/variants/careena/mainboard.c
new file mode 100644
index 0000000..c873299
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/mainboard.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/variants.h>
+
+uint8_t variant_board_sku(void)
+{
+ static int sku = -1;
+
+ if (sku == -1)
+ sku = google_chromeec_get_sku_id();
+
+ return sku;
+}
diff --git a/src/mainboard/google/kahlee/variants/careena/romstage.c b/src/mainboard/google/kahlee/variants/careena/romstage.c
new file mode 100644
index 0000000..2b8baf8
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/careena/romstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Google, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+
+void variant_romstage_entry(int s3_resume)
+{
+ uint32_t sku = google_chromeec_get_sku_id();
+
+ /* Based on SKU, turn on keyboard backlight to show system is booting */
+ if (sku <= 6 && !s3_resume)
+ google_chromeec_kbbacklight(75);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87a24f6d8115aacf5b21181f3820cf2718ad252a
Gerrit-Change-Number: 26524
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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