[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720

[Simon Glass (Code Review)]

Simon Glass has uploaded this change for review. ( https://review.coreboot.org/26515


Change subject: mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720
......................................................................

mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720

Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power.

BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046ffff

With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff

Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg at chromium.org>
---
M src/mainboard/google/kahlee/mainboard.c
M src/soc/amd/stoneyridge/include/soc/southbridge.h
2 files changed, 16 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26515/1

diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index a01ae0a..c543e10 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,6 +18,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <arch/acpi.h>
+#include <arch/io.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/amd_pci_util.h>
 #include <cbmem.h>
@@ -175,10 +176,17 @@
 	/* Initialize i2c busses that were not initialized in bootblock */
 	i2c_soc_init();
 
-	/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
-	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))
+	if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) {
+		/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
 		pm_write8(PM_PCIB_CFG,
 				pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
+
+		/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
+		clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
+				GPP_CLK3_CLOCK_REQ_MAP_MASK,
+				GPP_CLK3_CLOCK_REQ_MAP_CLK_REQ2 <<
+				GPP_CLK3_CLOCK_REQ_MAP_SHIFT);
+	}
 }
 
 /*************************************************
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 0a23fca..d0f2742 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -354,6 +354,12 @@
 #define   FCH_AOAC_STAT0		BIT(6)
 #define   FCH_AOAC_STAT1		BIT(7)
 
+/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */
+#define GPP_CLK_CNTRL			0
+#define GPP_CLK3_CLOCK_REQ_MAP_SHIFT	12
+#define GPP_CLK3_CLOCK_REQ_MAP_MASK	(0xf << GPP_CLK3_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK3_CLOCK_REQ_MAP_CLK_REQ2	3
+
 struct soc_amd_gpio {
 	uint8_t gpio;
 	uint8_t function;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Gerrit-Change-Number: 26515
Gerrit-PatchSet: 1
Gerrit-Owner: Simon Glass <sjg at chromium.org>
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