<p>Simon Glass has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26515">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720<br><br>Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to<br>save power.<br><br>BUG=b:73726008<br>BRANCH=none<br>TEST=boot without this patch:<br>$ iotools mem_read32 0xfed80e00<br>0x0046ffff<br><br>With this patch:<br>$ iotools mem_read32 0xfed80e00<br>0x00463fff<br><br>Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480<br>Signed-off-by: Simon Glass <sjg@chromium.org><br>---<br>M src/mainboard/google/kahlee/mainboard.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>2 files changed, 16 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/26515/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c</span><br><span>index a01ae0a..c543e10 100644</span><br><span>--- a/src/mainboard/google/kahlee/mainboard.c</span><br><span>+++ b/src/mainboard/google/kahlee/mainboard.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span> #include <amdblocks/agesawrapper.h></span><br><span> #include <amdblocks/amd_pci_util.h></span><br><span> #include <cbmem.h></span><br><span>@@ -175,10 +176,17 @@</span><br><span> /* Initialize i2c busses that were not initialized in bootblock */</span><br><span> i2c_soc_init();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */</span><br><span style="color: hsl(0, 100%, 40%);">- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */</span><br><span> pm_write8(PM_PCIB_CFG,</span><br><span> pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */</span><br><span style="color: hsl(120, 100%, 40%);">+ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK3_CLOCK_REQ_MAP_MASK,</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK3_CLOCK_REQ_MAP_CLK_REQ2 <<</span><br><span style="color: hsl(120, 100%, 40%);">+ GPP_CLK3_CLOCK_REQ_MAP_SHIFT);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> /*************************************************</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 0a23fca..d0f2742 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -354,6 +354,12 @@</span><br><span> #define FCH_AOAC_STAT0 BIT(6)</span><br><span> #define FCH_AOAC_STAT1 BIT(7)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK_CNTRL 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK3_CLOCK_REQ_MAP_SHIFT 12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK3_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK3_CLOCK_REQ_MAP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CLK3_CLOCK_REQ_MAP_CLK_REQ2 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> struct soc_amd_gpio {</span><br><span> uint8_t gpio;</span><br><span> uint8_t function;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26515">change 26515</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26515"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 </div>
<div style="display:none"> Gerrit-Change-Number: 26515 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Simon Glass <sjg@chromium.org> </div>