[coreboot-gerrit] Change in coreboot[master]: HACK: Julius' extra hacks for Cheza bring-up images
Julius Werner (Code Review)
gerrit at coreboot.org
Wed May 23 01:45:27 CEST 2018
Julius Werner has uploaded this change for review. ( https://review.coreboot.org/26489
Change subject: HACK: Julius' extra hacks for Cheza bring-up images
......................................................................
HACK: Julius' extra hacks for Cheza bring-up images
Not for review or submission. Just sharing some WIP code.
Change-Id: Ie59bc30bab88abfa17fa031b1be814c834192891
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/arch/arm64/arm_tf.c
M src/mainboard/google/cheza/Kconfig
M src/mainboard/google/cheza/Makefile.inc
M src/mainboard/google/cheza/mainboard.c
M src/mainboard/google/cheza/qupv3_config.c
M src/soc/qualcomm/sdm845/Makefile.inc
M src/soc/qualcomm/sdm845/include/soc/memlayout.ld
7 files changed, 22 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/26489/1
diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
index a172d42..f658ffe 100644
--- a/src/arch/arm64/arm_tf.c
+++ b/src/arch/arm64/arm_tf.c
@@ -88,6 +88,7 @@
/* MMU disable will flush cache, so passed params land in memory. */
raw_write_daif(SPSR_EXCEPTION_MASK);
mmu_disable();
+ dcache_clean_invalidate_all();
bl31_entry(&bl31_params, bl31_plat_params);
die("BL31 returned!");
}
diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig
index 8b1771f..9882b59 100644
--- a/src/mainboard/google/cheza/Kconfig
+++ b/src/mainboard/google/cheza/Kconfig
@@ -12,7 +12,6 @@
select SPI_FLASH
select SPI_FLASH_WINBOND
select MAINBOARD_HAS_CHROMEOS
- select HAVE_LINEAR_FRAMEBUFFER
config CONSOLE_UART_ADDR
hex
diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc
index b1f5190..9abc08a 100644
--- a/src/mainboard/google/cheza/Makefile.inc
+++ b/src/mainboard/google/cheza/Makefile.inc
@@ -15,3 +15,4 @@
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += framebuffer.c
+ramstage-y += qupv3_config.c
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
index fffa9c3..f47d5d7 100644
--- a/src/mainboard/google/cheza/mainboard.c
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <bootblock_common.h>
+#include <soc/qupv3_fw_config.h>
#include <timestamp.h>
#include <soc/usb.h>
@@ -29,7 +30,16 @@
static void mainboard_init(struct device *dev)
{
+ qupv3_fw_init();
setup_usb();
+ write32((void *)0x117048, 0x21);
+ write32((void *)0x1172a8, 0x21);
+ write32((void *)0x1173d8, 0x21);
+ write32((void *)0x117638, 0x21);
+ write32((void *)0x11828c, 0x21);
+ write32((void *)0x1183bc, 0x21);
+ write32((void *)0x1184ec, 0x21);
+ write32((void *)0x11874c, 0x21);
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/cheza/qupv3_config.c b/src/mainboard/google/cheza/qupv3_config.c
index 6d1d08f..5473dac 100644
--- a/src/mainboard/google/cheza/qupv3_config.c
+++ b/src/mainboard/google/cheza/qupv3_config.c
@@ -18,13 +18,17 @@
struct se_cfg se_mappings[QUPV3_SE_MAX] =
{
{QUPV3_0_SE0, SE_PROTOCOL_SPI, MIXED , true }, /* Fingerprint SPI */
- {QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED , true }, /* Touch I2C */
+ {QUPV3_0_SE2, SE_PROTOCOL_SPI, MIXED , true }, /* ESIM SPI */
{QUPV3_0_SE3, SE_PROTOCOL_I2C, MIXED , true }, /* EDP Bridge I2C */
- {QUPV3_0_SE5, SE_PROTOCOL_I2C, MIXED , true }, /* HP (codec) I2C */
+ {QUPV3_0_SE5, SE_PROTOCOL_SPI, MIXED , true }, /* H1 SPI */
+#ifndef __RAMSTAGE__
{QUPV3_0_SE6, SE_PROTOCOL_UART, FIFO , false}, /* BT UART */
{QUPV3_1_SE1, SE_PROTOCOL_UART, FIFO , false}, /* Debug UART */
- {QUPV3_1_SE3, SE_PROTOCOL_SPI, MIXED , true }, /* ESIM SPI */
+#endif
+ {QUPV3_1_SE2, SE_PROTOCOL_SPI, MIXED , true }, /* EC SPI */
+ {QUPV3_1_SE3, SE_PROTOCOL_I2C, MIXED , true }, /* Pen Detect I2C */
{QUPV3_1_SE4, SE_PROTOCOL_I2C, MIXED , true }, /* Speaker Amps I2C */
+ {QUPV3_1_SE6, SE_PROTOCOL_I2C, MIXED , true }, /* Touch I2C */
};
struct se_cfg *qupv3_get_se_mappings(void)
diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index 1864469..9fbd1e9 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -45,6 +45,7 @@
ramstage-y += gpio.c
ramstage-y += clock.c
ramstage-y += aop_load_reset.c
+ramstage-y += qupv3_fw_config.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-$(CONFIG_SPI_FLASH) += qspi.c
ramstage-$(CONFIG_QC_FLASH_SIMULATE_SDCARD) += fs_sdcard.c
diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
index a39760b..3ae2d82 100644
--- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
@@ -42,8 +42,8 @@
BSRAM_START(0x14800000)
REGION(fw_reserved2, 0x14800000, 0x16000, 4096)
- BOOTBLOCK(0x14816000, 32K)
- TTB(0x1481E000, 64K)
+ BOOTBLOCK(0x14816000, 40K)
+ TTB(0x14820000, 56K)
VBOOT2_WORK(0x1482E000, 16K)
STACK(0x14832000, 16K)
TIMESTAMP(0x14836000, 1K)
--
To view, visit https://review.coreboot.org/26489
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie59bc30bab88abfa17fa031b1be814c834192891
Gerrit-Change-Number: 26489
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
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