[coreboot-gerrit] Change in coreboot[master]: mainboard/amd/south_station: Fix coding style
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue May 22 15:00:12 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26466
Change subject: mainboard/amd/south_station: Fix coding style
......................................................................
mainboard/amd/south_station: Fix coding style
Change-Id: Iae457237ef104736478eface4d91dd282fd866ea
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/amd/south_station/BiosCallOuts.c
M src/mainboard/amd/south_station/OemCustomize.c
M src/mainboard/amd/south_station/acpi_tables.c
M src/mainboard/amd/south_station/buildOpts.c
M src/mainboard/amd/south_station/irq_tables.c
M src/mainboard/amd/south_station/mainboard.c
M src/mainboard/amd/south_station/mptable.c
M src/mainboard/amd/south_station/platform_cfg.h
8 files changed, 311 insertions(+), 320 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26466/1
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index 5b5e034..d25256c 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -20,183 +20,183 @@
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
#include <stdlib.h>
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data,
+ VOID * ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data,
+ VOID * ConfigPtr);
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
- {AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD, agesa_ReadSpd },
- {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
- {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
- {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },
- {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },
- {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+ {AGESA_DO_RESET, agesa_Reset},
+ {AGESA_READ_SPD, agesa_ReadSpd},
+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported},
+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp},
+ {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset},
+ {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit},
+ {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess},
+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess},
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess},
};
+
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data,
+ VOID * ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- MEM_DATA_STRUCT *MemData;
- UINT32 AcpiMmioAddr;
- UINT32 GpioMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
- UINT8 TempData8;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ MEM_DATA_STRUCT *MemData;
+ UINT32 AcpiMmioAddr;
+ UINT32 GpioMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
+ UINT8 TempData8;
- FcnData = Data;
- MemData = ConfigPtr;
+ FcnData = Data;
+ MemData = ConfigPtr;
- Status = AGESA_SUCCESS;
- /* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ Status = AGESA_SUCCESS;
+ /* Get SB MMIO Base (AcpiMmioAddr) */
+ WriteIo8(0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16 = Data8 << 8;
+ WriteIo8(0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16 |= Data8;
+ AcpiMmioAddr = (UINT32) Data16 << 16;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ Data8 &= ~BIT5;
+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ TempData8 &= 0x03;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+ Data8 |= BIT2 + BIT3;
+ Data8 &= ~BIT4;
+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ TempData8 &= 0x23;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~BIT5;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x03;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ Data8 &= ~BIT5;
+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ TempData8 &= 0x03;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
- Data8 |= BIT2+BIT3;
- Data8 &= ~BIT4;
- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- TempData8 &= 0x23;
- TempData8 |= Data8;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+ Data8 |= BIT2 + BIT3;
+ Data8 &= ~BIT4;
+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ TempData8 &= 0x23;
+ TempData8 |= Data8;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
- switch(MemData->ParameterListPtr->DDR3Voltage){
- case VOLT1_35:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_25:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- break;
- case VOLT1_5:
- default:
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
- Data8 |= (UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
- }
- return Status;
+ switch (MemData->ParameterListPtr->DDR3Voltage) {
+ case VOLT1_35:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ Data8 |= (UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_25:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
+ break;
+ case VOLT1_5:
+ default:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
+ Data8 |= (UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
+ }
+ return Status;
}
/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data,
+ VOID * ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- PCIe_SLOT_RESET_INFO *ResetInfo;
+ AGESA_STATUS Status;
+ UINTN FcnData;
+ PCIe_SLOT_RESET_INFO *ResetInfo;
- UINT32 GpioMmioAddr;
- UINT32 AcpiMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
+ UINT32 GpioMmioAddr;
+ UINT32 AcpiMmioAddr;
+ UINT8 Data8;
+ UINT16 Data16;
- FcnData = Data;
- ResetInfo = ConfigPtr;
- // Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch (ResetInfo->ResetId)
- {
- case 4:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 6:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 7:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 &= ~(UINT8)BIT6;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 |= BIT6;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- }
- return Status;
+ FcnData = Data;
+ ResetInfo = ConfigPtr;
+ // Get SB800 MMIO Base (AcpiMmioAddr)
+ WriteIo8(0xCD6, 0x27);
+ Data8 = ReadIo8(0xCD7);
+ Data16 = Data8 << 8;
+ WriteIo8(0xCD6, 0x26);
+ Data8 = ReadIo8(0xCD7);
+ Data16 |= Data8;
+ AcpiMmioAddr = (UINT32) Data16 << 16;
+ Status = AGESA_UNSUPPORTED;
+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+ switch (ResetInfo->ResetId) {
+ case 4:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ case 6:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ case 7:
+ switch (ResetInfo->ResetControl) {
+ case AssertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
+ Data8 &= ~(UINT8) BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Status = AGESA_SUCCESS;
+ break;
+ case DeassertSlotReset:
+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
+ Data8 |= BIT6;
+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
+ Status = AGESA_SUCCESS;
+ break;
+ }
+ break;
+ }
+ return Status;
}
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
index 45c9f11..a75383f 100644
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ b/src/mainboard/amd/south_station/OemCustomize.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#include <AGESA.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <PlatformMemoryConfiguration.h>
@@ -21,82 +20,72 @@
static const PCIe_PORT_DESCRIPTOR PortList[] = {
// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
{
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 4)
- },
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+ HotplugDisabled, PcieGen2, PcieGen2,
+ AspmL0sL1, 4)
+ },
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 5)
- },
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
+ HotplugDisabled, PcieGen2, PcieGen2,
+ AspmL0sL1, 5)
+ },
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 6)
- },
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
+ HotplugDisabled, PcieGen2, PcieGen2,
+ AspmL0sL1, 6)
+ },
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 7)
- },
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
+ HotplugDisabled, PcieGen2, PcieGen2,
+ AspmL0sL1, 7)
+ },
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
{
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
- HotplugDisabled,
- PcieGen2,
- PcieGen2,
- AspmL0sL1, 0)
- }
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+ HotplugDisabled, PcieGen2, PcieGen2,
+ AspmL0sL1, 0)
+ }
};
static const PCIe_DDI_DESCRIPTOR DdiList[] = {
/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
{
- 0,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
- },
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
+ },
/* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
{
- DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
- }
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
+ }
};
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
- .Flags = DESCRIPTOR_TERMINATE_LIST,
- .SocketId = 0,
+ .Flags = DESCRIPTOR_TERMINATE_LIST,
+ .SocketId = 0,
.PciePortList = PortList,
- .DdiLinkList = DdiList,
+ .DdiLinkList = DdiList,
};
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
- InitEarly->GnbConfig.PsppPolicy = 0;
+ InitEarly->GnbConfig.PsppPolicy = 0;
}
/*----------------------------------------------------------------------------------------
@@ -111,12 +100,13 @@
* use its default conservative settings.
*/
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
- NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
- PSO_END
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+ PSO_END
};
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
- InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+ InitPost->MemConfig.PlatformMemoryConfiguration =
+ (PSO_ENTRY *) PlatformMemoryTable;
}
diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c
index 2aaa608..78aa582 100644
--- a/src/mainboard/amd/south_station/acpi_tables.c
+++ b/src/mainboard/amd/south_station/acpi_tables.c
@@ -28,12 +28,12 @@
/* Write SB800 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
+ current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
+ current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
index 68236b6..e168f94 100644
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ b/src/mainboard/amd/south_station/buildOpts.c
@@ -27,7 +27,6 @@
#include <stdlib.h>
-
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
@@ -80,12 +79,12 @@
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
- #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
- #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
- #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
- #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
- #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
- #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
+#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
#define BLDOPT_REMOVE_SRAT TRUE
#define BLDOPT_REMOVE_SLIT TRUE
#define BLDOPT_REMOVE_WHEA TRUE
@@ -99,7 +98,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -204,20 +202,19 @@
#include "AGESA.h"
/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
- { CPU_LIST_TERMINAL }
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = {
+ {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
+ {AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull},
+ {AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull},
+ {CPU_LIST_TERMINAL}
};
/* Include the files that instantiate the configuration definitions. */
@@ -247,37 +244,37 @@
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 // DDR 400
+#define DDR533_FREQUENCY 266 // DDR 533
+#define DDR667_FREQUENCY 333 // DDR 667
+#define DDR800_FREQUENCY 400 // DDR 800
+#define DDR1066_FREQUENCY 533 // DDR 1066
+#define DDR1333_FREQUENCY 667 // DDR 1333
+#define DDR1600_FREQUENCY 800 // DDR 1600
+#define DDR1866_FREQUENCY 933 // DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY 934 // Highest limit of DDR frequency
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 // Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 // Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 // Use best rate possible
+#define TIMING_MODE_LIMITED 1 // Set user top limit
+#define TIMING_MODE_SPECIFIC 2 // Set user specified speed
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 // Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 // Chip select power down mode
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c
index 9ebe58a..b5fd355 100644
--- a/src/mainboard/amd/south_station/irq_tables.c
+++ b/src/mainboard/amd/south_station/irq_tables.c
@@ -78,9 +78,8 @@
slot_num = 0;
/* pci bridge */
- write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
- 0);
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2,
+ 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++;
slot_num++;
@@ -92,12 +91,10 @@
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) {
+ if (sum != pirq->checksum)
pirq->checksum = sum;
- }
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
-
}
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index d069838..c60ee86 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -18,7 +18,7 @@
#include <device/device.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" /* Platform Specific Definitions */
/**
* Southstation using SB GPIO 17/18 to control the Red/Green LED
@@ -26,32 +26,39 @@
*/
static void southstation_led_init(void)
{
-#define GPIO_FUNCTION 2 //GPIO function
-#define SB_GPIO_REG17 17 //Red Light
-#define SB_GPIO_REG18 18 //Green Light
+#define GPIO_FUNCTION 2 //GPIO function
+#define SB_GPIO_REG17 17 //Red Light
+#define SB_GPIO_REG18 18 //Green Light
/* multi-function pins switch to GPIO0-35 */
- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8,
+ ~BIT0, 1);
/* select IOMux to function2, corresponds to GPIO */
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8,
+ ~(BIT0 | BIT1), GPIO_FUNCTION);
+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8,
+ ~(BIT0 | BIT1), GPIO_FUNCTION);
/* Lighting test */
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8,
+ ~(0xFF), 0x08); //output high
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8,
+ ~(0xFF), 0x08);
mdelay(100);
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8,
+ ~(0xFF), 0x48); //output low
+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8,
+ ~(0xFF), 0x48);
}
-
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(struct device *dev)
{
- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ printk(BIOS_INFO,
+ "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
southstation_led_init();
/*
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 152b959..c8d6033 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
@@ -23,15 +22,18 @@
#include <stdint.h>
#include <SBPLATFORM.h>
-
u8 intr_data[] = {
- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x10,0x11,0x12,0x13
+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */
+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x12, 0x13
};
static void *smp_write_config_table(void *v)
@@ -61,7 +63,7 @@
u8 byte;
- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ for (byte = 0x0; byte < sizeof(intr_data); byte++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
@@ -76,9 +78,9 @@
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
- /* APU Internal Graphic Device*/
+ /* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
index d39a3ab..43f4fc5 100644
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ b/src/mainboard/amd/south_station/platform_cfg.h
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
@@ -27,7 +26,7 @@
*/
#ifndef BIOS_SIZE
#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
+#endif /* BIOS_SIZE */
/**
* @def SPREAD_SPECTRUM
@@ -35,7 +34,7 @@
* 0 - Disable Spread Spectrum function
* 1 - Enable Spread Spectrum function
*/
-#define SPREAD_SPECTRUM 0
+#define SPREAD_SPECTRUM 0
/**
* @def SB_HPET_TIMER
@@ -43,7 +42,7 @@
* 0 - Disable hpet
* 1 - Enable hpet
*/
-#define HPET_TIMER 1
+#define HPET_TIMER 1
/**
* @def USB_CONFIG
@@ -58,7 +57,7 @@
* Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
* Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
*/
-#define USB_CONFIG 0x7F
+#define USB_CONFIG 0x7F
/**
* @def PCI_CLOCK_CTRL
@@ -71,33 +70,33 @@
* PCI SLOT 3 define at BIT3
* PCI SLOT 4 define at BIT4
*/
-#define PCI_CLOCK_CTRL 0x1F
+#define PCI_CLOCK_CTRL 0x1F
/**
* @def SATA_CONTROLLER
* @brief INCHIP Sata Controller
*/
-#define SATA_CONTROLLER CIMX_OPTION_ENABLED
+#define SATA_CONTROLLER CIMX_OPTION_ENABLED
/**
* @def SATA_MODE
* @brief INCHIP Sata Controller Mode
* NOTE: DO NOT ALLOW SATA & IDE use same mode
*/
-#define SATA_MODE CONFIG_SB800_SATA_MODE
+#define SATA_MODE CONFIG_SB800_SATA_MODE
/**
* @brief INCHIP Sata IDE Controller Mode
*/
-#define IDE_LEGACY_MODE 0
-#define IDE_NATIVE_MODE 1
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
/**
* @def SATA_IDE_MODE
* @brief INCHIP Sata IDE Controller Mode
* NOTE: DO NOT ALLOW SATA & IDE use same mode
*/
-#define SATA_IDE_MODE IDE_LEGACY_MODE
+#define SATA_IDE_MODE IDE_LEGACY_MODE
/**
* @def EXTERNAL_CLOCK
@@ -108,8 +107,8 @@
* @brief 01/11: Reference clock from internal clock through
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
*/
-#define EXTERNAL_CLOCK 0x00
-#define INTERNAL_CLOCK 0x01
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
/* NOTE: inagua have to using internal clock,
* otherwise can not detect sata drive
@@ -122,7 +121,6 @@
*/
#define SATA_PORT_MULT_CAP_RESERVED 1
-
/**
* @def AZALIA_AUTO
* @brief Detect Azalia controller automatically.
@@ -133,14 +131,14 @@
* @def AZALIA_ENABLE
* @brief Enable Azalia controller.
*/
-#define AZALIA_AUTO 0
-#define AZALIA_DISABLE 1
-#define AZALIA_ENABLE 2
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
/**
* @brief INCHIP HDA controller
*/
-#define AZALIA_CONTROLLER AZALIA_AUTO
+#define AZALIA_CONTROLLER AZALIA_AUTO
/**
* @def AZALIA_PIN_CONFIG
@@ -148,7 +146,7 @@
* 0 - disable
* 1 - enable
*/
-#define AZALIA_PIN_CONFIG 1
+#define AZALIA_PIN_CONFIG 1
/**
* @def AZALIA_SDIN_PIN
@@ -161,13 +159,13 @@
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
-//#define AZALIA_SDIN_PIN 0xAA
-#define AZALIA_SDIN_PIN 0x2A
+//#define AZALIA_SDIN_PIN 0xAA
+#define AZALIA_SDIN_PIN 0x2A
/**
* @def GPP_CONTROLLER
*/
-#define GPP_CONTROLLER CIMX_OPTION_ENABLED
+#define GPP_CONTROLLER CIMX_OPTION_ENABLED
/**
* @def GPP_CFGMODE
@@ -178,34 +176,34 @@
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
-#define GPP_CFGMODE GPP_CFGMODE_X1111
+#define GPP_CFGMODE GPP_CFGMODE_X1111
/**
* @def NB_SB_GEN2
* 0 - Disable
* 1 - Enable
*/
-#define NB_SB_GEN2 TRUE
+#define NB_SB_GEN2 TRUE
/**
* @def SB_GPP_GEN2
* 0 - Disable
* 1 - Enable
*/
-#define SB_GPP_GEN2 TRUE
+#define SB_GPP_GEN2 TRUE
/**
* @def SB_GPP_UNHIDE_PORTS
* TRUE - ports visible always, even port empty
* FALSE - ports invisible if port empty
*/
-#define SB_GPP_UNHIDE_PORTS FALSE
+#define SB_GPP_UNHIDE_PORTS FALSE
/**
* @def GEC_CONFIG
* 0 - Enable
* 1 - Disable
*/
-#define GEC_CONFIG 0
+#define GEC_CONFIG 0
#endif
--
To view, visit https://review.coreboot.org/26466
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iae457237ef104736478eface4d91dd282fd866ea
Gerrit-Change-Number: 26466
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180522/7b6ea249/attachment-0001.html>
More information about the coreboot-gerrit
mailing list