<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26466">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/amd/south_station: Fix coding style<br><br>Change-Id: Iae457237ef104736478eface4d91dd282fd866ea<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/amd/south_station/BiosCallOuts.c<br>M src/mainboard/amd/south_station/OemCustomize.c<br>M src/mainboard/amd/south_station/acpi_tables.c<br>M src/mainboard/amd/south_station/buildOpts.c<br>M src/mainboard/amd/south_station/irq_tables.c<br>M src/mainboard/amd/south_station/mainboard.c<br>M src/mainboard/amd/south_station/mptable.c<br>M src/mainboard/amd/south_station/platform_cfg.h<br>8 files changed, 311 insertions(+), 320 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26466/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c</span><br><span>index 5b5e034..d25256c 100644</span><br><span>--- a/src/mainboard/amd/south_station/BiosCallOuts.c</span><br><span>+++ b/src/mainboard/amd/south_station/BiosCallOuts.c</span><br><span>@@ -20,183 +20,183 @@</span><br><span> #include <southbridge/amd/cimx/sb800/gpio_oem.h></span><br><span> #include <stdlib.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);</span><br><span style="color: hsl(0, 100%, 40%);">-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data,</span><br><span style="color: hsl(120, 100%, 40%);">+ VOID * ConfigPtr);</span><br><span style="color: hsl(120, 100%, 40%);">+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data,</span><br><span style="color: hsl(120, 100%, 40%);">+ VOID * ConfigPtr);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-const BIOS_CALLOUT_STRUCT BiosCallouts[] =</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_DO_RESET, agesa_Reset },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_READ_SPD, agesa_ReadSpd },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },</span><br><span style="color: hsl(0, 100%, 40%);">- {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },</span><br><span style="color: hsl(120, 100%, 40%);">+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_DO_RESET, agesa_Reset},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_READ_SPD, agesa_ReadSpd},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess},</span><br><span> };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);</span><br><span> </span><br><span> /* Call the host environment interface to provide a user hook opportunity. */</span><br><span style="color: hsl(0, 100%, 40%);">-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)</span><br><span style="color: hsl(120, 100%, 40%);">+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data,</span><br><span style="color: hsl(120, 100%, 40%);">+ VOID * ConfigPtr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- AGESA_STATUS Status;</span><br><span style="color: hsl(0, 100%, 40%);">- UINTN FcnData;</span><br><span style="color: hsl(0, 100%, 40%);">- MEM_DATA_STRUCT *MemData;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 AcpiMmioAddr;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GpioMmioAddr;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Data16;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 TempData8;</span><br><span style="color: hsl(120, 100%, 40%);">+ AGESA_STATUS Status;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINTN FcnData;</span><br><span style="color: hsl(120, 100%, 40%);">+ MEM_DATA_STRUCT *MemData;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 AcpiMmioAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GpioMmioAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Data16;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TempData8;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- FcnData = Data;</span><br><span style="color: hsl(0, 100%, 40%);">- MemData = ConfigPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ FcnData = Data;</span><br><span style="color: hsl(120, 100%, 40%);">+ MemData = ConfigPtr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get SB MMIO Base (AcpiMmioAddr) */</span><br><span style="color: hsl(0, 100%, 40%);">- WriteIo8 (0xCD6, 0x27);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(0, 100%, 40%);">- Data16 = Data8 << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- WriteIo8 (0xCD6, 0x26);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(0, 100%, 40%);">- Data16 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- AcpiMmioAddr = (UINT32)Data16 << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Get SB MMIO Base (AcpiMmioAddr) */</span><br><span style="color: hsl(120, 100%, 40%);">+ WriteIo8(0xCD6, 0x27);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data16 = Data8 << 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ WriteIo8(0xCD6, 0x26);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data16 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ AcpiMmioAddr = (UINT32) Data16 << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~BIT5;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 &= 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~BIT5;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 &= 0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= BIT2+BIT3;</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~BIT4;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 &= 0x23;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= BIT2 + BIT3;</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~BIT4;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 &= 0x23;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~BIT5;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 &= 0x03;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~BIT5;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 &= 0x03;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= BIT2+BIT3;</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~BIT4;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 &= 0x23;</span><br><span style="color: hsl(0, 100%, 40%);">- TempData8 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= BIT2 + BIT3;</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~BIT4;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 &= 0x23;</span><br><span style="color: hsl(120, 100%, 40%);">+ TempData8 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- switch(MemData->ParameterListPtr->DDR3Voltage){</span><br><span style="color: hsl(0, 100%, 40%);">- case VOLT1_35:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= (UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case VOLT1_25:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case VOLT1_5:</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= (UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return Status;</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (MemData->ParameterListPtr->DDR3Voltage) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case VOLT1_35:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= (UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case VOLT1_25:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case VOLT1_5:</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= (UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return Status;</span><br><span> }</span><br><span> </span><br><span> /* PCIE slot reset control */</span><br><span style="color: hsl(0, 100%, 40%);">-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)</span><br><span style="color: hsl(120, 100%, 40%);">+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data,</span><br><span style="color: hsl(120, 100%, 40%);">+ VOID * ConfigPtr)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- AGESA_STATUS Status;</span><br><span style="color: hsl(0, 100%, 40%);">- UINTN FcnData;</span><br><span style="color: hsl(0, 100%, 40%);">- PCIe_SLOT_RESET_INFO *ResetInfo;</span><br><span style="color: hsl(120, 100%, 40%);">+ AGESA_STATUS Status;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINTN FcnData;</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIe_SLOT_RESET_INFO *ResetInfo;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 GpioMmioAddr;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 AcpiMmioAddr;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT16 Data16;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 GpioMmioAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 AcpiMmioAddr;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT16 Data16;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- FcnData = Data;</span><br><span style="color: hsl(0, 100%, 40%);">- ResetInfo = ConfigPtr;</span><br><span style="color: hsl(0, 100%, 40%);">- // Get SB800 MMIO Base (AcpiMmioAddr)</span><br><span style="color: hsl(0, 100%, 40%);">- WriteIo8(0xCD6, 0x27);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(0, 100%, 40%);">- Data16 = Data8 << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- WriteIo8(0xCD6, 0x26);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(0, 100%, 40%);">- Data16 |= Data8;</span><br><span style="color: hsl(0, 100%, 40%);">- AcpiMmioAddr = (UINT32)Data16 << 16;</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_UNSUPPORTED;</span><br><span style="color: hsl(0, 100%, 40%);">- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;</span><br><span style="color: hsl(0, 100%, 40%);">- switch (ResetInfo->ResetId)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- case 4:</span><br><span style="color: hsl(0, 100%, 40%);">- switch (ResetInfo->ResetControl)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- case AssertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case DeassertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 6:</span><br><span style="color: hsl(0, 100%, 40%);">- switch (ResetInfo->ResetControl)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- case AssertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case DeassertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case 7:</span><br><span style="color: hsl(0, 100%, 40%);">- switch (ResetInfo->ResetControl)</span><br><span style="color: hsl(0, 100%, 40%);">- {</span><br><span style="color: hsl(0, 100%, 40%);">- case AssertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 &= ~(UINT8)BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- case DeassertSlotReset:</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);</span><br><span style="color: hsl(0, 100%, 40%);">- Data8 |= BIT6;</span><br><span style="color: hsl(0, 100%, 40%);">- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</span><br><span style="color: hsl(0, 100%, 40%);">- Status = AGESA_SUCCESS;</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return Status;</span><br><span style="color: hsl(120, 100%, 40%);">+ FcnData = Data;</span><br><span style="color: hsl(120, 100%, 40%);">+ ResetInfo = ConfigPtr;</span><br><span style="color: hsl(120, 100%, 40%);">+ // Get SB800 MMIO Base (AcpiMmioAddr)</span><br><span style="color: hsl(120, 100%, 40%);">+ WriteIo8(0xCD6, 0x27);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data16 = Data8 << 8;</span><br><span style="color: hsl(120, 100%, 40%);">+ WriteIo8(0xCD6, 0x26);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = ReadIo8(0xCD7);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data16 |= Data8;</span><br><span style="color: hsl(120, 100%, 40%);">+ AcpiMmioAddr = (UINT32) Data16 << 16;</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_UNSUPPORTED;</span><br><span style="color: hsl(120, 100%, 40%);">+ GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (ResetInfo->ResetId) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 4:</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (ResetInfo->ResetControl) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case AssertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case DeassertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 6:</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (ResetInfo->ResetControl) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case AssertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case DeassertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 7:</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (ResetInfo->ResetControl) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case AssertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 &= ~(UINT8) BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case DeassertSlotReset:</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);</span><br><span style="color: hsl(120, 100%, 40%);">+ Data8 |= BIT6;</span><br><span style="color: hsl(120, 100%, 40%);">+ Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02</span><br><span style="color: hsl(120, 100%, 40%);">+ Status = AGESA_SUCCESS;</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return Status;</span><br><span> }</span><br><span>diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c</span><br><span>index 45c9f11..a75383f 100644</span><br><span>--- a/src/mainboard/amd/south_station/OemCustomize.c</span><br><span>+++ b/src/mainboard/amd/south_station/OemCustomize.c</span><br><span>@@ -13,7 +13,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <AGESA.h></span><br><span> #include <northbridge/amd/agesa/state_machine.h></span><br><span> #include <PlatformMemoryConfiguration.h></span><br><span>@@ -21,82 +20,72 @@</span><br><span> static const PCIe_PORT_DESCRIPTOR PortList[] = {</span><br><span> // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 4)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, PcieGen2, PcieGen2,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 5)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, PcieGen2, PcieGen2,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, 5)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 6)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, PcieGen2, PcieGen2,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, 6)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 7)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, PcieGen2, PcieGen2,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, 7)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,</span><br><span style="color: hsl(0, 100%, 40%);">- HotplugDisabled,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- PcieGen2,</span><br><span style="color: hsl(0, 100%, 40%);">- AspmL0sL1, 0)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,</span><br><span style="color: hsl(120, 100%, 40%);">+ HotplugDisabled, PcieGen2, PcieGen2,</span><br><span style="color: hsl(120, 100%, 40%);">+ AspmL0sL1, 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> };</span><br><span> </span><br><span> static const PCIe_DDI_DESCRIPTOR DdiList[] = {</span><br><span> /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- 0,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)</span><br><span style="color: hsl(0, 100%, 40%);">- },</span><br><span style="color: hsl(120, 100%, 40%);">+ 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),</span><br><span style="color: hsl(0, 100%, 40%);">- PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),</span><br><span style="color: hsl(120, 100%, 40%);">+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> };</span><br><span> </span><br><span> static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {</span><br><span style="color: hsl(0, 100%, 40%);">- .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(0, 100%, 40%);">- .SocketId = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .Flags = DESCRIPTOR_TERMINATE_LIST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .SocketId = 0,</span><br><span> .PciePortList = PortList,</span><br><span style="color: hsl(0, 100%, 40%);">- .DdiLinkList = DdiList,</span><br><span style="color: hsl(120, 100%, 40%);">+ .DdiLinkList = DdiList,</span><br><span> };</span><br><span> </span><br><span> void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)</span><br><span> {</span><br><span> InitEarly->GnbConfig.PcieComplexList = &PcieComplex;</span><br><span style="color: hsl(0, 100%, 40%);">- InitEarly->GnbConfig.PsppPolicy = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ InitEarly->GnbConfig.PsppPolicy = 0;</span><br><span> }</span><br><span> </span><br><span> /*----------------------------------------------------------------------------------------</span><br><span>@@ -111,12 +100,13 @@</span><br><span> * use its default conservative settings.</span><br><span> */</span><br><span> static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),</span><br><span style="color: hsl(0, 100%, 40%);">- NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),</span><br><span style="color: hsl(0, 100%, 40%);">- PSO_END</span><br><span style="color: hsl(120, 100%, 40%);">+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),</span><br><span style="color: hsl(120, 100%, 40%);">+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),</span><br><span style="color: hsl(120, 100%, 40%);">+ PSO_END</span><br><span> };</span><br><span> </span><br><span> void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;</span><br><span style="color: hsl(120, 100%, 40%);">+ InitPost->MemConfig.PlatformMemoryConfiguration =</span><br><span style="color: hsl(120, 100%, 40%);">+ (PSO_ENTRY *) PlatformMemoryTable;</span><br><span> }</span><br><span>diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c</span><br><span>index 2aaa608..78aa582 100644</span><br><span>--- a/src/mainboard/amd/south_station/acpi_tables.c</span><br><span>+++ b/src/mainboard/amd/south_station/acpi_tables.c</span><br><span>@@ -28,12 +28,12 @@</span><br><span> </span><br><span> /* Write SB800 IOAPIC, only one */</span><br><span> current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,</span><br><span style="color: hsl(0, 100%, 40%);">- CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);</span><br><span> </span><br><span> current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(0, 100%, 40%);">- current, 0, 0, 2, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 0, 2, 0);</span><br><span> current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(0, 100%, 40%);">- current, 0, 9, 9, 0xF);</span><br><span style="color: hsl(120, 100%, 40%);">+ current, 0, 9, 9, 0xF);</span><br><span> </span><br><span> /* 0: mean bus 0--->ISA */</span><br><span> /* 0: PIC 0 */</span><br><span>diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c</span><br><span>index 68236b6..e168f94 100644</span><br><span>--- a/src/mainboard/amd/south_station/buildOpts.c</span><br><span>+++ b/src/mainboard/amd/south_station/buildOpts.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> </span><br><span> #include <stdlib.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Select the CPU family. */</span><br><span> #define INSTALL_FAMILY_10_SUPPORT FALSE</span><br><span> #define INSTALL_FAMILY_12_SUPPORT FALSE</span><br><span>@@ -80,12 +79,12 @@</span><br><span> #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE</span><br><span> #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE</span><br><span> #define BLDOPT_REMOVE_ACPI_PSTATES FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE</span><br><span style="color: hsl(0, 100%, 40%);">- #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE</span><br><span> #define BLDOPT_REMOVE_SRAT TRUE</span><br><span> #define BLDOPT_REMOVE_SLIT TRUE</span><br><span> #define BLDOPT_REMOVE_WHEA TRUE</span><br><span>@@ -99,7 +98,6 @@</span><br><span> #define BLDOPT_REMOVE_GFX_RECOVERY TRUE</span><br><span> #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS</span><br><span> #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER</span><br><span> </span><br><span>@@ -204,20 +202,19 @@</span><br><span> #include "AGESA.h"</span><br><span> </span><br><span> /* The fixed MTRR values to be set after memory initialization. */</span><br><span style="color: hsl(0, 100%, 40%);">-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },</span><br><span style="color: hsl(0, 100%, 40%);">- { CPU_LIST_TERMINAL }</span><br><span style="color: hsl(120, 100%, 40%);">+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull},</span><br><span style="color: hsl(120, 100%, 40%);">+ {CPU_LIST_TERMINAL}</span><br><span> };</span><br><span> </span><br><span> /* Include the files that instantiate the configuration definitions. */</span><br><span>@@ -247,37 +244,37 @@</span><br><span> * version string as appropriate for the release. The trunk copy of this file</span><br><span> * should also be updated/incremented for the next expected version, + trailing 'X'</span><br><span> ****************************************************************************/</span><br><span style="color: hsl(0, 100%, 40%);">- // This is the delivery package title, "BrazosPI"</span><br><span style="color: hsl(0, 100%, 40%);">- // This string MUST be exactly 8 characters long</span><br><span style="color: hsl(120, 100%, 40%);">+ // This is the delivery package title, "BrazosPI"</span><br><span style="color: hsl(120, 100%, 40%);">+ // This string MUST be exactly 8 characters long</span><br><span> #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- // This is the release version number of the AGESA component</span><br><span style="color: hsl(0, 100%, 40%);">- // This string MUST be exactly 12 characters long</span><br><span style="color: hsl(120, 100%, 40%);">+ // This is the release version number of the AGESA component</span><br><span style="color: hsl(120, 100%, 40%);">+ // This string MUST be exactly 12 characters long</span><br><span> #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}</span><br><span> </span><br><span> /* MEMORY_BUS_SPEED */</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR400_FREQUENCY 200 ///< DDR 400</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR533_FREQUENCY 266 ///< DDR 533</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR667_FREQUENCY 333 ///< DDR 667</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR800_FREQUENCY 400 ///< DDR 800</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR1066_FREQUENCY 533 ///< DDR 1066</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR1333_FREQUENCY 667 ///< DDR 1333</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR1600_FREQUENCY 800 ///< DDR 1600</span><br><span style="color: hsl(0, 100%, 40%);">-#define DDR1866_FREQUENCY 933 ///< DDR 1866</span><br><span style="color: hsl(0, 100%, 40%);">-#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR400_FREQUENCY 200 // DDR 400</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR533_FREQUENCY 266 // DDR 533</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR667_FREQUENCY 333 // DDR 667</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR800_FREQUENCY 400 // DDR 800</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR1066_FREQUENCY 533 // DDR 1066</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR1333_FREQUENCY 667 // DDR 1333</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR1600_FREQUENCY 800 // DDR 1600</span><br><span style="color: hsl(120, 100%, 40%);">+#define DDR1866_FREQUENCY 933 // DDR 1866</span><br><span style="color: hsl(120, 100%, 40%);">+#define UNSUPPORTED_DDR_FREQUENCY 934 // Highest limit of DDR frequency</span><br><span> </span><br><span> /* QUANDRANK_TYPE*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM</span><br><span style="color: hsl(0, 100%, 40%);">-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM</span><br><span style="color: hsl(120, 100%, 40%);">+#define QUADRANK_REGISTERED 0 // Quadrank registered DIMM</span><br><span style="color: hsl(120, 100%, 40%);">+#define QUADRANK_UNBUFFERED 1 // Quadrank unbuffered DIMM</span><br><span> </span><br><span> /* USER_MEMORY_TIMING_MODE */</span><br><span style="color: hsl(0, 100%, 40%);">-#define TIMING_MODE_AUTO 0 ///< Use best rate possible</span><br><span style="color: hsl(0, 100%, 40%);">-#define TIMING_MODE_LIMITED 1 ///< Set user top limit</span><br><span style="color: hsl(0, 100%, 40%);">-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed</span><br><span style="color: hsl(120, 100%, 40%);">+#define TIMING_MODE_AUTO 0 // Use best rate possible</span><br><span style="color: hsl(120, 100%, 40%);">+#define TIMING_MODE_LIMITED 1 // Set user top limit</span><br><span style="color: hsl(120, 100%, 40%);">+#define TIMING_MODE_SPECIFIC 2 // Set user specified speed</span><br><span> </span><br><span> /* POWER_DOWN_MODE */</span><br><span style="color: hsl(0, 100%, 40%);">-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode</span><br><span style="color: hsl(0, 100%, 40%);">-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define POWER_DOWN_BY_CHANNEL 0 // Channel power down mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define POWER_DOWN_BY_CHIP_SELECT 1 // Chip select power down mode</span><br><span> </span><br><span> // The following definitions specify the default values for various parameters in which there are</span><br><span> // no clearly defined defaults to be used in the common file. The values below are based on product</span><br><span>diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c</span><br><span>index 9ebe58a..b5fd355 100644</span><br><span>--- a/src/mainboard/amd/south_station/irq_tables.c</span><br><span>+++ b/src/mainboard/amd/south_station/irq_tables.c</span><br><span>@@ -78,9 +78,8 @@</span><br><span> slot_num = 0;</span><br><span> </span><br><span> /* pci bridge */</span><br><span style="color: hsl(0, 100%, 40%);">- write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,</span><br><span style="color: hsl(0, 100%, 40%);">- 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);</span><br><span> pirq_info++;</span><br><span> </span><br><span> slot_num++;</span><br><span>@@ -92,12 +91,10 @@</span><br><span> </span><br><span> sum = pirq->checksum - sum;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (sum != pirq->checksum) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (sum != pirq->checksum)</span><br><span> pirq->checksum = sum;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span> </span><br><span> printk(BIOS_INFO, "write_pirq_routing_table done.\n");</span><br><span> </span><br><span> return (unsigned long)pirq_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> }</span><br><span>diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c</span><br><span>index d069838..c60ee86 100644</span><br><span>--- a/src/mainboard/amd/south_station/mainboard.c</span><br><span>+++ b/src/mainboard/amd/south_station/mainboard.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platform Specific Definitions */</span><br><span> </span><br><span> /**</span><br><span> * Southstation using SB GPIO 17/18 to control the Red/Green LED</span><br><span>@@ -26,32 +26,39 @@</span><br><span> */</span><br><span> static void southstation_led_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_FUNCTION 2 //GPIO function</span><br><span style="color: hsl(0, 100%, 40%);">-#define SB_GPIO_REG17 17 //Red Light</span><br><span style="color: hsl(0, 100%, 40%);">-#define SB_GPIO_REG18 18 //Green Light</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_FUNCTION 2 //GPIO function</span><br><span style="color: hsl(120, 100%, 40%);">+#define SB_GPIO_REG17 17 //Red Light</span><br><span style="color: hsl(120, 100%, 40%);">+#define SB_GPIO_REG18 18 //Green Light</span><br><span> </span><br><span> /* multi-function pins switch to GPIO0-35 */</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~BIT0, 1);</span><br><span> </span><br><span> /* select IOMux to function2, corresponds to GPIO */</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(BIT0 | BIT1), GPIO_FUNCTION);</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(BIT0 | BIT1), GPIO_FUNCTION);</span><br><span> </span><br><span> /* Lighting test */</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(0xFF), 0x08); //output high</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(0xFF), 0x08);</span><br><span> mdelay(100);</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low</span><br><span style="color: hsl(0, 100%, 40%);">- RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(0xFF), 0x48); //output low</span><br><span style="color: hsl(120, 100%, 40%);">+ RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8,</span><br><span style="color: hsl(120, 100%, 40%);">+ ~(0xFF), 0x48);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**********************************************</span><br><span> * Enable the dedicated functions of the board.</span><br><span> **********************************************/</span><br><span> static void mainboard_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO,</span><br><span style="color: hsl(120, 100%, 40%);">+ "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");</span><br><span> southstation_led_init();</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c</span><br><span>index 152b959..c8d6033 100644</span><br><span>--- a/src/mainboard/amd/south_station/mptable.c</span><br><span>+++ b/src/mainboard/amd/south_station/mptable.c</span><br><span>@@ -13,7 +13,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #include <console/console.h></span><br><span> #include <arch/smp/mpspec.h></span><br><span> #include <device/pci.h></span><br><span>@@ -23,15 +22,18 @@</span><br><span> #include <stdint.h></span><br><span> #include <SBPLATFORM.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> u8 intr_data[] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */</span><br><span style="color: hsl(0, 100%, 40%);">- [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */</span><br><span style="color: hsl(0, 100%, 40%);">- [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,</span><br><span style="color: hsl(0, 100%, 40%);">- 0x10,0x11,0x12,0x13</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil,0,1,2, INT from Serial irq */</span><br><span style="color: hsl(120, 100%, 40%);">+ [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10, 0x11, 0x12, 0x13</span><br><span> };</span><br><span> </span><br><span> static void *smp_write_config_table(void *v)</span><br><span>@@ -61,7 +63,7 @@</span><br><span> </span><br><span> u8 byte;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- for (byte = 0x0; byte < sizeof(intr_data); byte ++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ for (byte = 0x0; byte < sizeof(intr_data); byte++) {</span><br><span> outb(byte | 0x80, 0xC00);</span><br><span> outb(intr_data[byte], 0xC01);</span><br><span> }</span><br><span>@@ -76,9 +78,9 @@</span><br><span> * associated with a specific bus/device/function tuple.</span><br><span> */</span><br><span> #define PCI_INT(bus, dev, fn, pin) \</span><br><span style="color: hsl(0, 100%, 40%);">- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))</span><br><span style="color: hsl(120, 100%, 40%);">+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* APU Internal Graphic Device*/</span><br><span style="color: hsl(120, 100%, 40%);">+ /* APU Internal Graphic Device */</span><br><span> PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);</span><br><span> PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);</span><br><span> </span><br><span>diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h</span><br><span>index d39a3ab..43f4fc5 100644</span><br><span>--- a/src/mainboard/amd/south_station/platform_cfg.h</span><br><span>+++ b/src/mainboard/amd/south_station/platform_cfg.h</span><br><span>@@ -13,7 +13,6 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> #ifndef _PLATFORM_CFG_H_</span><br><span> #define _PLATFORM_CFG_H_</span><br><span> </span><br><span>@@ -27,7 +26,7 @@</span><br><span> */</span><br><span> #ifndef BIOS_SIZE</span><br><span> #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)</span><br><span style="color: hsl(0, 100%, 40%);">-#endif /* BIOS_SIZE */</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* BIOS_SIZE */</span><br><span> </span><br><span> /**</span><br><span> * @def SPREAD_SPECTRUM</span><br><span>@@ -35,7 +34,7 @@</span><br><span> * 0 - Disable Spread Spectrum function</span><br><span> * 1 - Enable Spread Spectrum function</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPREAD_SPECTRUM 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPREAD_SPECTRUM 0</span><br><span> </span><br><span> /**</span><br><span> * @def SB_HPET_TIMER</span><br><span>@@ -43,7 +42,7 @@</span><br><span> * 0 - Disable hpet</span><br><span> * 1 - Enable hpet</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define HPET_TIMER 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define HPET_TIMER 1</span><br><span> </span><br><span> /**</span><br><span> * @def USB_CONFIG</span><br><span>@@ -58,7 +57,7 @@</span><br><span> * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5</span><br><span> * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define USB_CONFIG 0x7F</span><br><span style="color: hsl(120, 100%, 40%);">+#define USB_CONFIG 0x7F</span><br><span> </span><br><span> /**</span><br><span> * @def PCI_CLOCK_CTRL</span><br><span>@@ -71,33 +70,33 @@</span><br><span> * PCI SLOT 3 define at BIT3</span><br><span> * PCI SLOT 4 define at BIT4</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCI_CLOCK_CTRL 0x1F</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCI_CLOCK_CTRL 0x1F</span><br><span> </span><br><span> /**</span><br><span> * @def SATA_CONTROLLER</span><br><span> * @brief INCHIP Sata Controller</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SATA_CONTROLLER CIMX_OPTION_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATA_CONTROLLER CIMX_OPTION_ENABLED</span><br><span> </span><br><span> /**</span><br><span> * @def SATA_MODE</span><br><span> * @brief INCHIP Sata Controller Mode</span><br><span> * NOTE: DO NOT ALLOW SATA & IDE use same mode</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SATA_MODE CONFIG_SB800_SATA_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATA_MODE CONFIG_SB800_SATA_MODE</span><br><span> </span><br><span> /**</span><br><span> * @brief INCHIP Sata IDE Controller Mode</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_LEGACY_MODE 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define IDE_NATIVE_MODE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDE_LEGACY_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define IDE_NATIVE_MODE 1</span><br><span> </span><br><span> /**</span><br><span> * @def SATA_IDE_MODE</span><br><span> * @brief INCHIP Sata IDE Controller Mode</span><br><span> * NOTE: DO NOT ALLOW SATA & IDE use same mode</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SATA_IDE_MODE IDE_LEGACY_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define SATA_IDE_MODE IDE_LEGACY_MODE</span><br><span> </span><br><span> /**</span><br><span> * @def EXTERNAL_CLOCK</span><br><span>@@ -108,8 +107,8 @@</span><br><span> * @brief 01/11: Reference clock from internal clock through</span><br><span> * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define EXTERNAL_CLOCK 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-#define INTERNAL_CLOCK 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define EXTERNAL_CLOCK 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define INTERNAL_CLOCK 0x01</span><br><span> </span><br><span> /* NOTE: inagua have to using internal clock,</span><br><span> * otherwise can not detect sata drive</span><br><span>@@ -122,7 +121,6 @@</span><br><span> */</span><br><span> #define SATA_PORT_MULT_CAP_RESERVED 1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /**</span><br><span> * @def AZALIA_AUTO</span><br><span> * @brief Detect Azalia controller automatically.</span><br><span>@@ -133,14 +131,14 @@</span><br><span> * @def AZALIA_ENABLE</span><br><span> * @brief Enable Azalia controller.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_AUTO 0</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_DISABLE 1</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_ENABLE 2</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_AUTO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_DISABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_ENABLE 2</span><br><span> </span><br><span> /**</span><br><span> * @brief INCHIP HDA controller</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_CONTROLLER AZALIA_AUTO</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_CONTROLLER AZALIA_AUTO</span><br><span> </span><br><span> /**</span><br><span> * @def AZALIA_PIN_CONFIG</span><br><span>@@ -148,7 +146,7 @@</span><br><span> * 0 - disable</span><br><span> * 1 - enable</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_PIN_CONFIG 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_PIN_CONFIG 1</span><br><span> </span><br><span> /**</span><br><span> * @def AZALIA_SDIN_PIN</span><br><span>@@ -161,13 +159,13 @@</span><br><span> * SDIN2 is define at BIT4 & BIT5</span><br><span> * SDIN3 is define at BIT6 & BIT7</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-//#define AZALIA_SDIN_PIN 0xAA</span><br><span style="color: hsl(0, 100%, 40%);">-#define AZALIA_SDIN_PIN 0x2A</span><br><span style="color: hsl(120, 100%, 40%);">+//#define AZALIA_SDIN_PIN 0xAA</span><br><span style="color: hsl(120, 100%, 40%);">+#define AZALIA_SDIN_PIN 0x2A</span><br><span> </span><br><span> /**</span><br><span> * @def GPP_CONTROLLER</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CONTROLLER CIMX_OPTION_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CONTROLLER CIMX_OPTION_ENABLED</span><br><span> </span><br><span> /**</span><br><span> * @def GPP_CFGMODE</span><br><span>@@ -178,34 +176,34 @@</span><br><span> * GPP_CFGMODE_X2110</span><br><span> * GPP_CFGMODE_X1111</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPP_CFGMODE GPP_CFGMODE_X1111</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPP_CFGMODE GPP_CFGMODE_X1111</span><br><span> </span><br><span> /**</span><br><span> * @def NB_SB_GEN2</span><br><span> * 0 - Disable</span><br><span> * 1 - Enable</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_SB_GEN2 TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_SB_GEN2 TRUE</span><br><span> </span><br><span> /**</span><br><span> * @def SB_GPP_GEN2</span><br><span> * 0 - Disable</span><br><span> * 1 - Enable</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SB_GPP_GEN2 TRUE</span><br><span style="color: hsl(120, 100%, 40%);">+#define SB_GPP_GEN2 TRUE</span><br><span> </span><br><span> /**</span><br><span> * @def SB_GPP_UNHIDE_PORTS</span><br><span> * TRUE - ports visible always, even port empty</span><br><span> * FALSE - ports invisible if port empty</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define SB_GPP_UNHIDE_PORTS FALSE</span><br><span style="color: hsl(120, 100%, 40%);">+#define SB_GPP_UNHIDE_PORTS FALSE</span><br><span> </span><br><span> /**</span><br><span> * @def GEC_CONFIG</span><br><span> * 0 - Enable</span><br><span> * 1 - Disable</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-#define GEC_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define GEC_CONFIG 0</span><br><span> </span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26466">change 26466</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26466"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iae457237ef104736478eface4d91dd282fd866ea </div>
<div style="display:none"> Gerrit-Change-Number: 26466 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>