[coreboot-gerrit] Change in coreboot[master]: src: Add space after 'switch'
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue May 22 13:33:06 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26463
Change subject: src: Add space after 'switch'
......................................................................
src: Add space after 'switch'
Change-Id: Ieddcd3d0742bc91283212e1b5ddf4a4521fd2d70
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/amd/south_station/BiosCallOuts.c
M src/mainboard/amd/union_station/BiosCallOuts.c
M src/mainboard/asrock/e350m1/BiosCallOuts.c
M src/soc/broadcom/cygnus/shmoo_and28.c
4 files changed, 29 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/26463/1
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index 5b5e034..e80cb73 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -91,7 +91,7 @@
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
- switch(MemData->ParameterListPtr->DDR3Voltage){
+ switch (MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index 5b5e034..e80cb73 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -91,7 +91,7 @@
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
- switch(MemData->ParameterListPtr->DDR3Voltage){
+ switch (MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 1f1e929..32a289d 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -90,7 +90,7 @@
/* this seems to be just copy-pasted from the AMD reference boards and needs
* some investigation
*/
- switch(MemData->ParameterListPtr->DDR3Voltage){
+ switch (MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
diff --git a/src/soc/broadcom/cygnus/shmoo_and28.c b/src/soc/broadcom/cygnus/shmoo_and28.c
index 7038a31..68938dd 100644
--- a/src/soc/broadcom/cygnus/shmoo_and28.c
+++ b/src/soc/broadcom/cygnus/shmoo_and28.c
@@ -1160,7 +1160,7 @@
yCapMin = (*scPtr).yCapMin;
yCapMax = (*scPtr).yCapMax;
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
iter = shmoo_dram_info_ptr->interface_bitwidth;
@@ -1337,7 +1337,7 @@
switch ((*scPtr).shmooType) {
case SHMOO_AND28_RD_EN:
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
@@ -1466,7 +1466,7 @@
}
#endif
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
@@ -1838,7 +1838,7 @@
}
break;
case SHMOO_AND28_WR_EXTENDED:
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
@@ -2053,7 +2053,7 @@
}
break;
case SHMOO_AND28_ADDR_EXTENDED:
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
@@ -2117,7 +2117,7 @@
}
else
{
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
@@ -2257,13 +2257,13 @@
printf("\n\n");
- switch(plotMode)
+ switch (plotMode)
{
case SHMOO_AND28_BIT:
iter = shmoo_dram_info_ptr->interface_bitwidth;
shiftAmount = 0;
dataMask = 0x1;
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
calibShiftAmount = 0;
@@ -2286,7 +2286,7 @@
iter = shmoo_dram_info_ptr->interface_bitwidth >> 3;
shiftAmount = 3;
dataMask = 0xFF;
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("WARNING: Plot mode coerced from byte mode to bit mode\n");
@@ -2313,7 +2313,7 @@
iter = shmoo_dram_info_ptr->interface_bitwidth >> 4;
shiftAmount = 4;
dataMask = 0xFFFF;
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("WARNING: Plot mode coerced from halfword mode to bit mode\n");
@@ -2344,7 +2344,7 @@
iter = 1;
shiftAmount = 5;
dataMask = 0xFFFFFFFF;
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf("WARNING: Plot mode coerced from word mode to bit mode\n");
@@ -2427,7 +2427,7 @@
printf(" **** VDL step size...: %3u.%03u ps\n", (step1000 / 1000), (step1000 % 1000));
printf(" **** UI size.........: %3u.%03u steps\n", (size1000UI / 1000), (size1000UI % 1000));
- switch((*scPtr).shmooType)
+ switch ((*scPtr).shmooType)
{
case SHMOO_AND28_RD_EN:
printf(" **** Shmoo type......: RD_EN\n");
@@ -2462,7 +2462,7 @@
if (sizeY > 1)
{
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf(" *** Calib mode......: 2D Bit-wise\n");
@@ -2481,7 +2481,7 @@
return SOC_E_FAIL;
}
- switch(plotMode)
+ switch (plotMode)
{
case SHMOO_AND28_BIT:
printf(" *** Plot mode.......: 2D Bit-wise\n");
@@ -2567,7 +2567,7 @@
{
if (i == 0)
{
- switch(calibMode)
+ switch (calibMode)
{
case SHMOO_AND28_BIT:
printf(" *** Calib mode......: 1D Bit-wise\n");
@@ -2586,7 +2586,7 @@
return SOC_E_FAIL;
}
- switch(plotMode)
+ switch (plotMode)
{
case SHMOO_AND28_BIT:
printf(" *** Plot mode.......: 1D Bit-wise\n");
@@ -4298,7 +4298,7 @@
if (action == SHMOO_AND28_ACTION_RESTORE)
{
- switch(ctlType)
+ switch (ctlType)
{
case SHMOO_AND28_CTL_TYPE_RSVP:
break;
@@ -4318,12 +4318,12 @@
}
else if ((action == SHMOO_AND28_ACTION_RUN) || (action == SHMOO_AND28_ACTION_RUN_AND_SAVE))
{
- switch(ctlType)
+ switch (ctlType)
{
case SHMOO_AND28_CTL_TYPE_RSVP:
break;
case SHMOO_AND28_CTL_TYPE_1:
- switch(dramType)
+ switch (dramType)
{
#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3)
case SHMOO_AND28_DRAM_TYPE_DDR3:
@@ -4409,7 +4409,7 @@
else
{
/* Report only */
- switch(ctlType)
+ switch (ctlType)
{
case SHMOO_AND28_CTL_TYPE_RSVP:
break;
@@ -4464,7 +4464,7 @@
return SOC_E_FAIL;
}
- switch(shmoo_dram_info_ptr->data_rate_mbps)
+ switch (shmoo_dram_info_ptr->data_rate_mbps)
{
case 800:
pll_config = 0x018D0012;
@@ -4607,7 +4607,7 @@
/*A02*/ printf("A02. Configure timing parameters\n");
if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
{
- switch(shmoo_dram_info_ptr->data_rate_mbps)
+ switch (shmoo_dram_info_ptr->data_rate_mbps)
{
case 800:
dram_timing1 = 0x0F040606;
@@ -4640,7 +4640,7 @@
}
else
{
- switch(shmoo_dram_info_ptr->data_rate_mbps)
+ switch (shmoo_dram_info_ptr->data_rate_mbps)
{
case 800:
dram_timing1 = 0x0F040606;
@@ -4675,7 +4675,7 @@
dram_config = 0x00001000;
if (!SHMOO_AND28_PHY_BITWIDTH_IS_32)
dram_config |= 0x02000000;
- switch(shmoo_dram_info_ptr->num_rows)
+ switch (shmoo_dram_info_ptr->num_rows)
{
case 4096: dram_config |= 0x00000000; break;
case 8192: dram_config |= 0x00000010; break;
@@ -4686,7 +4686,7 @@
printf("Unsupported number of rows: %d\n", shmoo_dram_info_ptr->num_rows);
return SOC_E_FAIL;
}
- switch(shmoo_dram_info_ptr->num_columns)
+ switch (shmoo_dram_info_ptr->num_columns)
{
case 512: dram_config |= 0x00000000; break;
case 1024: dram_config |= 0x00000100; break;
@@ -4695,7 +4695,7 @@
printf("Unsupported number of columns: %d\n", shmoo_dram_info_ptr->num_columns);
return SOC_E_FAIL;
}
- switch(shmoo_dram_info_ptr->num_banks)
+ switch (shmoo_dram_info_ptr->num_banks)
{
case 4: dram_config |= 0x00000000; break;
case 8: dram_config |= 0x00000400; break;
--
To view, visit https://review.coreboot.org/26463
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ieddcd3d0742bc91283212e1b5ddf4a4521fd2d70
Gerrit-Change-Number: 26463
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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