[coreboot-gerrit] Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue May 22 13:06:35 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26461
Change subject: src: Use "foo *bar" instead of "foo* bar"
......................................................................
src: Use "foo *bar" instead of "foo* bar"
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/drivers/amd/agesa/eventlog.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kfsn4-dre_k8/romstage.c
M src/mainboard/intel/kunimitsu/spd/spd_util.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdht/h3finit.h
M src/northbridge/amd/pi/agesawrapper_call.h
M src/northbridge/intel/fsp_sandybridge/raminit.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/soc/intel/baytrail/include/soc/gpio.h
M src/soc/intel/fsp_baytrail/include/soc/gpio.h
M src/soc/nvidia/tegra210/clock.c
M src/soc/nvidia/tegra210/include/soc/clock.h
M src/southbridge/amd/sb700/sm.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_i89xx/me_8.x.c
18 files changed, 38 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/26461/1
diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
index 33e5590..f6f6383 100644
--- a/src/drivers/amd/agesa/eventlog.c
+++ b/src/drivers/amd/agesa/eventlog.c
@@ -84,9 +84,9 @@
* 0x6 = AGESA_CRITICAL
* 0x7 = AGESA_FATAL
*/
-static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
+static const char *decodeAGESA_STATUS(AGESA_STATUS sret)
{
- const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
+ const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
"AGESA_BOUNDS_CHK", "AGESA_ALERT",
"AGESA_WARNING", "AGESA_ERROR",
"AGESA_CRITICAL", "AGESA_FATAL"
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 105dacf..2249139 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -118,7 +118,7 @@
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */
};
-static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id)
+static void ck804_control(const unsigned int *values, u32 size, uint8_t bus_unit_id)
{
unsigned busn[4], io_base[4];
int i, ck804_num = 0;
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
index a404b06..a7ed9f7 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
@@ -122,7 +122,7 @@
RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */
};
-static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id)
+static void ck804_control(const unsigned int *values, u32 size, uint8_t bus_unit_id)
{
unsigned busn[4], io_base[4];
int i, ck804_num = 0;
diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c
index a17b519..676f84d 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd_util.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c
@@ -75,7 +75,7 @@
uintptr_t mainboard_get_spd_data(void)
{
- char* spd_file;
+ char *spd_file;
int spd_index, spd_span;
size_t spd_file_len;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index f50c2ee..e647579 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1040,7 +1040,7 @@
}
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
-static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *current)
+static int amdfam10_get_smbios_data16(int *count, int handle, unsigned long *current)
{
struct amdmct_memory_info *mem_info;
mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
@@ -1145,7 +1145,7 @@
}
}
-static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, unsigned long *current)
+static int amdfam10_get_smbios_data17(int *count, int handle, int parent_handle, unsigned long *current)
{
struct amdmct_memory_info *mem_info;
mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO);
diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h
index 45ed3c1..743ae97 100644
--- a/src/northbridge/amd/amdht/h3finit.h
+++ b/src/northbridge/amd/amdht/h3finit.h
@@ -168,7 +168,7 @@
* @param[in] u8 node = The node on which this chain is located
* @param[in] u8 link = The link on the host for this chain
* @param[out] u8 secBus = Secondary Bus number for this non-coherent chain
- * @param[out] u8* subBus = Subordinate Bus number
+ * @param[out] u8 *subBus = Subordinate Bus number
* @param[out] BOOL result = true this routine is supplying the bus numbers
* false use auto Bus numbering
*
@@ -194,7 +194,7 @@
* Parameters:
* @param[in] u8 node = The node on which this chain is located
* @param[in] u8 link = The link on the host for this chain
- * @param[out] u8** list = supply a pointer to a list
+ * @param[out] u8 **list = supply a pointer to a list
* @param[out] BOOL result = true to use a manual list
* false to initialize the link automatically
*
@@ -226,10 +226,10 @@
* @param[in] u8 Dev = The Device's PCI device Number
* @param[in] u32 DevVenID = The Device's PCI Vendor + Device ID (offset 0x00)
* @param[in] u8 Link = The Device's link number (0 or 1)
- * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
- * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
- * @param[in,out] u32* FreqCap = modify to change the link's frequency capability
- * @param[in,out] u32* FeatureCap = modify to change the link's feature capability
+ * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In
+ * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out
+ * @param[in,out] u32 *FreqCap = modify to change the link's frequency capability
+ * @param[in,out] u32 *FeatureCap = modify to change the link's feature capability
*
* ---------------------------------------------------------------------------------------
*/
@@ -266,9 +266,9 @@
* @param[in] u8 linkA = The link on this node
* @param[in] u8 nodeB = The other node on which this link is located
* @param[in] u8 linkB = The link on that node
- * @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In
- * @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out
- * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability
+ * @param[in,out] u8 *ABLinkWidthLimit = modify to change the Link Witdh In
+ * @param[in,out] u8 *BALinkWidthLimit = modify to change the Link Witdh Out
+ * @param[in,out] u32 *PCBFreqCap = modify to change the link's frequency capability
*
* ---------------------------------------------------------------------------------------
*/
@@ -299,9 +299,9 @@
* @param[in] u8 hostNode = The node on which this link is located
* @param[in] u8 hostLink = The link about to be initialized
* @param[in] u8 Depth = The depth in the I/O chain from the Host
- * @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In
- * @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out
- * @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability
+ * @param[in,out] u8 *DownstreamLinkWidthLimit = modify to change the Link Witdh In
+ * @param[in,out] u8 *UpstreamLinkWidthLimit = modify to change the Link Witdh Out
+ * @param[in,out] u32 *PCBFreqCap = modify to change the link's frequency capability
*
* ---------------------------------------------------------------------------------------
*/
@@ -400,9 +400,9 @@
* @param[in] u8 hostLink = The link about to be initialized
* @param[in] u8 Depth = The depth in the I/O chain from the Host
* @param[in] u8 Link = the link on the device (0 or 1)
- * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
- * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
- * @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
+ * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In
+ * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out
+ * @param[in,out] u16 *LinkFrequency = modify to change the link's frequency capability
*
* ---------------------------------------------------------------------------------------
*/
@@ -431,9 +431,9 @@
* Parameters:
* @param[in] u8 node = One node on which this link is located
* @param[in] u8 link = The link on this node
- * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
- * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
- * @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability
+ * @param[in,out] u8 *LinkWidthIn = modify to change the Link Witdh In
+ * @param[in,out] u8 *LinkWidthOut = modify to change the Link Witdh Out
+ * @param[in,out] u16 *LinkFrequency = modify to change the link's frequency capability
*
*---------------------------------------------------------------------------------------
*/
@@ -459,7 +459,7 @@
* Parameters:
* @param[in] u8 evtClass = What level event is this
* @param[in] u16 event = A unique ID of this event
- * @param[in] u8* pEventData0 = useful data associated with the event.
+ * @param[in] u8 *pEventData0 = useful data associated with the event.
*
* ---------------------------------------------------------------------------------------
*/
diff --git a/src/northbridge/amd/pi/agesawrapper_call.h b/src/northbridge/amd/pi/agesawrapper_call.h
index 15b9098..1ed4a4c 100644
--- a/src/northbridge/amd/pi/agesawrapper_call.h
+++ b/src/northbridge/amd/pi/agesawrapper_call.h
@@ -32,7 +32,7 @@
*/
static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
{
- const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
+ const char *statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
"AGESA_BOUNDS_CHK", "AGESA_ALERT",
"AGESA_WARNING", "AGESA_ERROR",
"AGESA_CRITICAL", "AGESA_FATAL"
diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c
index 7cc61ae..f67d405 100644
--- a/src/northbridge/intel/fsp_sandybridge/raminit.c
+++ b/src/northbridge/intel/fsp_sandybridge/raminit.c
@@ -21,7 +21,7 @@
#include "raminit.h"
#include "northbridge.h"
-static const char* ecc_decoder[] = {
+static const char *ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index e5e2b93..55a7339 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -62,7 +62,7 @@
__func__, pei_data->mrc_input, pei_data->mrc_input_len);
}
-static const char* ecc_decoder[] = {
+static const char *ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 61f761e..691452c 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -130,7 +130,7 @@
__func__, pei_data->mrc_input, pei_data->mrc_input_len);
}
-static const char* ecc_decoder[] = {
+static const char *ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h
index 0e0395a..580c4eb 100644
--- a/src/soc/intel/baytrail/include/soc/gpio.h
+++ b/src/soc/intel/baytrail/include/soc/gpio.h
@@ -366,7 +366,7 @@
/* Description of GPIO 'bank' ex. {ncore, score. ssus} */
struct gpio_bank {
const int gpio_count;
- const u8* gpio_to_pad;
+ const u8 *gpio_to_pad;
const int legacy_base;
const unsigned long pad_base;
const u8 has_wake_en :1;
diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 02c226b..7c81151 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -342,7 +342,7 @@
/* Description of GPIO 'bank' ex. {ncore, score. ssus} */
struct gpio_bank {
const int gpio_count;
- const u8* gpio_to_pad;
+ const u8 *gpio_to_pad;
const int legacy_base;
const unsigned long pad_base;
const u8 has_wake_en :1;
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index ba1efdc..86fbf6c 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -644,7 +644,7 @@
graphics_pll();
}
-void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
+void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg,
u32 *rst_dev_clr_reg)
{
write32(clk_enb_set_reg, val);
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index 46e1e96..1ae6ce1 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -431,7 +431,7 @@
void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y);
-void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
+void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg);
void clock_reset_l(u32 l);
void clock_reset_h(u32 h);
void clock_reset_u(u32 u);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 436854e..6211dde 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -48,7 +48,7 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON
#endif
-static const char* power_mode_names[] = {
+static const char *power_mode_names[] = {
[POWER_MODE_OFF] = "off",
[POWER_MODE_ON] = "on",
[POWER_MODE_LAST] = "last",
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 54a16ce..0334af3 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -830,7 +830,7 @@
memset(mbp_data, 0, sizeof(*mbp_data));
while (mbp_hdr.num_entries--) {
- u32* copy_addr;
+ u32 *copy_addr;
u32 copy_size, buffer_room;
void *p;
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 03a9d45..fb68d6d 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -827,7 +827,7 @@
memset(mbp_data, 0, sizeof(*mbp_data));
while (mbp_hdr.num_entries--) {
- u32* copy_addr;
+ u32 *copy_addr;
u32 copy_size, buffer_room;
void *p;
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index b77cad2..e3e55e2 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -782,7 +782,7 @@
memset(mbp_data, 0, sizeof(*mbp_data));
while (mbp_hdr.num_entries--) {
- u32* copy_addr;
+ u32 *copy_addr;
u32 copy_size, buffer_room;
void *p;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8
Gerrit-Change-Number: 26461
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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