[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue May 22 10:48:38 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26457
Change subject: soc/intel/braswell: Get rid of device_t
......................................................................
soc/intel/braswell: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/include/soc/acpi.h
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/ramstage.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/scc.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/braswell/xhci.c
19 files changed, 59 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/26457/1
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index a672f7f..1aa6cf3 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -420,7 +420,7 @@
acpigen_pop_len();
}
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
@@ -482,7 +482,7 @@
return 0;
}
-unsigned long southcluster_write_acpi_tables(device_t device,
+unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@@ -524,7 +524,7 @@
return current;
}
-void southcluster_inject_dsdt(device_t device)
+void southcluster_inject_dsdt(struct device *device)
{
global_nvs_t *gnvs;
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 49e5ce6..35cbd15 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -23,7 +23,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -38,7 +38,7 @@
.scan_bus = pci_domain_scan_bus,
};
-static void cpu_bus_noop(device_t dev) { }
+static void cpu_bus_noop(struct device *dev) { }
static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
@@ -48,7 +48,7 @@
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",
__FILE__, __func__,
@@ -87,7 +87,7 @@
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
struct soc_intel_braswell_config *config;
if (!dev) {
@@ -382,7 +382,7 @@
.init = soc_init,
};
-static void pci_set_subsystem(device_t dev, unsigned int vendor,
+static void pci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
@@ -407,7 +407,7 @@
**/
int SocStepping(void)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
u8 revid = pci_read_config8(dev, 0x8);
switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index ed7e2fa..31b1b78 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -45,7 +45,7 @@
REG_SCRIPT_END
};
-static void soc_core_init(device_t cpu)
+static void soc_core_init(struct device *cpu)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(cpu));
@@ -215,7 +215,7 @@
.post_mp_init = southcluster_smm_enable_smi,
};
-void soc_init_cpus(device_t dev)
+void soc_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 9057953..44116a8 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -32,7 +32,7 @@
REG_SCRIPT_END,
};
-static void emmc_init(device_t dev)
+static void emmc_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 8481446..40bdf83 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -41,12 +41,12 @@
REG_SCRIPT_END
};
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
{
reg_script_run_on_dev(dev, ops);
}
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -54,7 +54,7 @@
gfx_run_script(dev, gpu_pre_vbios_script);
}
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -62,7 +62,7 @@
gfx_run_script(dev, gfx_post_vbios_script);
}
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 7f57727..162f81a 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -24,8 +24,8 @@
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
-void southcluster_inject_dsdt(device_t device);
-unsigned long southcluster_write_acpi_tables(device_t device,
+void southcluster_inject_dsdt(struct device *device);
+unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h
index 3f8249b..d735de5 100644
--- a/src/soc/intel/braswell/include/soc/ramstage.h
+++ b/src/soc/intel/braswell/include/soc/ramstage.h
@@ -96,10 +96,10 @@
* initialization, but it's after console and cbmem has been reinitialized.
*/
void soc_init_pre_device(struct soc_intel_braswell_config *config);
-void soc_init_cpus(device_t dev);
+void soc_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void southcluster_enable_dev(struct device *dev);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
int SocStepping(void);
void board_silicon_USB2_override(SILICON_INIT_UPD *params);
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 436099b..f8660bc 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -44,7 +44,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
-static void assign_device_nvs(device_t dev, u32 *field, unsigned int index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index)
{
struct resource *res;
@@ -53,7 +53,7 @@
*field = res->base;
}
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -87,7 +87,7 @@
reg_script_run_on_dev(dev, ops);
}
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
{
uint32_t reg;
u32 *clk_reg;
@@ -123,7 +123,7 @@
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
{
struct resource *res;
struct resource *mmio;
@@ -148,7 +148,7 @@
}
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
@@ -162,7 +162,7 @@
lpe_enable_acpi_mode(dev);
}
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
{
struct resource *res;
pci_dev_read_resources(dev);
@@ -184,7 +184,7 @@
FIRMWARE_PHYS_LENGTH >> 10);
}
-static void lpe_set_resources(device_t dev)
+static void lpe_set_resources(struct device *dev)
{
struct resource *res;
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index cbef92e..9248d82 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -30,7 +30,7 @@
#include "chip.h"
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -67,7 +67,7 @@
reg_script_run_on_dev(dev, ops);
}
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{
*iosf_reg = -1;
*nvs_index = -1;
@@ -110,7 +110,7 @@
}
}
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
{
/* Release the I2C devices from reset. */
static const struct reg_script ops[] = {
@@ -137,7 +137,7 @@
}
}
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
int iosf_reg, nvs_index;
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index dc72a46..3245a28 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -81,7 +81,7 @@
return tolm;
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
unsigned long mmconf;
unsigned long bmbound_k;
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index 9ea154a..1a127f4 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -29,17 +29,17 @@
static int pll_en_off;
static uint32_t strpfusecfg;
-static inline int root_port_offset(device_t dev)
+static inline int root_port_offset(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
-static inline int is_first_port(device_t dev)
+static inline int is_first_port(struct device *dev)
{
return root_port_offset(dev) == PCIE_PORT1_FUNC;
}
-static void pcie_init(device_t dev)
+static void pcie_init(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -52,7 +52,7 @@
REG_SCRIPT_END,
};
-static void check_port_enabled(device_t dev)
+static void check_port_enabled(struct device *dev)
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
@@ -81,10 +81,10 @@
}
}
-static void check_device_present(device_t dev)
+static void check_device_present(struct device *dev)
{
/* port1_dev will store the dev struct pointer of the PORT1 */
- static device_t port1_dev;
+ static struct device *port1_dev;
/*
* The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW.
@@ -135,7 +135,7 @@
}
}
-static void pcie_enable(device_t dev)
+static void pcie_enable(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -159,7 +159,7 @@
southcluster_enable_dev(dev);
}
-static void pcie_root_set_subsystem(device_t dev, unsigned int vid,
+static void pcie_root_set_subsystem(struct device *dev, unsigned int vid,
unsigned int did)
{
printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 1b71f92..3ab1af3 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -78,7 +78,7 @@
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c
index 42699f8..8052b29 100644
--- a/src/soc/intel/braswell/sata.c
+++ b/src/soc/intel/braswell/sata.c
@@ -34,7 +34,7 @@
__FILE__, __func__, dev_name(dev));
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
southcluster_enable_dev(dev);
}
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 6538c5c..122c67e 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -24,7 +24,7 @@
#include <soc/nvs.h>
#include <soc/ramstage.h>
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
global_nvs_t *gnvs;
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 4f192ab..97c39b3 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -31,7 +31,7 @@
#define CAP_OVERRIDE_HIGH 0xa4
# define USE_CAP_OVERRIDES (1 << 31)
-static void sd_init(device_t dev)
+static void sd_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 0f5c7c9..3c85b6d 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -70,7 +70,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 05fa855..85bb4af 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -53,14 +53,14 @@
}
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",
__FILE__, __func__, dev_name(dev), addr, size);
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -97,7 +97,7 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -113,7 +113,7 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
@@ -133,7 +133,7 @@
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -154,7 +154,7 @@
cmos_init(rtc_failure());
}
-static void sc_init(device_t dev)
+static void sc_init(struct device *dev)
{
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
@@ -198,7 +198,7 @@
*/
/* Set bit in function disble register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
@@ -287,7 +287,7 @@
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
@@ -304,7 +304,7 @@
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio.
*/
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
@@ -326,7 +326,7 @@
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned int offset;
@@ -405,7 +405,7 @@
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index b9e1627..3bf83d9 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -233,7 +233,7 @@
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
+ struct device *dev;
uint32_t sbase;
#if ENV_SMM
diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c
index 76319c0..49b6c4b 100644
--- a/src/soc/intel/braswell/xhci.c
+++ b/src/soc/intel/braswell/xhci.c
@@ -32,7 +32,7 @@
#include "chip.h"
-static void xhci_init(device_t dev)
+static void xhci_init(struct device *dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793
Gerrit-Change-Number: 26457
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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