<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26457">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/braswell/acpi.c<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/braswell/emmc.c<br>M src/soc/intel/braswell/gfx.c<br>M src/soc/intel/braswell/include/soc/acpi.h<br>M src/soc/intel/braswell/include/soc/ramstage.h<br>M src/soc/intel/braswell/lpe.c<br>M src/soc/intel/braswell/lpss.c<br>M src/soc/intel/braswell/northcluster.c<br>M src/soc/intel/braswell/pcie.c<br>M src/soc/intel/braswell/ramstage.c<br>M src/soc/intel/braswell/sata.c<br>M src/soc/intel/braswell/scc.c<br>M src/soc/intel/braswell/sd.c<br>M src/soc/intel/braswell/smihandler.c<br>M src/soc/intel/braswell/southcluster.c<br>M src/soc/intel/braswell/spi.c<br>M src/soc/intel/braswell/xhci.c<br>19 files changed, 59 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/26457/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c</span><br><span>index a672f7f..1aa6cf3 100644</span><br><span>--- a/src/soc/intel/braswell/acpi.c</span><br><span>+++ b/src/soc/intel/braswell/acpi.c</span><br><span>@@ -420,7 +420,7 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void generate_cpu_entries(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int core;</span><br><span> int pcontrol_blk = get_pmbase(), plen = 6;</span><br><span>@@ -482,7 +482,7 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southcluster_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southcluster_write_acpi_tables(struct device *device,</span><br><span> unsigned long current,</span><br><span> struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>@@ -524,7 +524,7 @@</span><br><span> return current;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_inject_dsdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_inject_dsdt(struct device *device)</span><br><span> {</span><br><span> global_nvs_t *gnvs;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c</span><br><span>index 49e5ce6..35cbd15 100644</span><br><span>--- a/src/soc/intel/braswell/chip.c</span><br><span>+++ b/src/soc/intel/braswell/chip.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/ramstage.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -38,7 +38,7 @@</span><br><span> .scan_bus = pci_domain_scan_bus,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void cpu_bus_noop(device_t dev) { }</span><br><span style="color: hsl(120, 100%, 40%);">+static void cpu_bus_noop(struct device *dev) { }</span><br><span> </span><br><span> static struct device_operations cpu_bus_ops = {</span><br><span> .read_resources = cpu_bus_noop,</span><br><span>@@ -48,7 +48,7 @@</span><br><span> };</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",</span><br><span> __FILE__, __func__,</span><br><span>@@ -87,7 +87,7 @@</span><br><span> </span><br><span> void soc_silicon_init_params(SILICON_INIT_UPD *params)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span> struct soc_intel_braswell_config *config;</span><br><span> </span><br><span> if (!dev) {</span><br><span>@@ -382,7 +382,7 @@</span><br><span> .init = soc_init,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_set_subsystem(device_t dev, unsigned int vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_set_subsystem(struct device *dev, unsigned int vendor,</span><br><span> unsigned int device)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",</span><br><span>@@ -407,7 +407,7 @@</span><br><span> **/</span><br><span> int SocStepping(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));</span><br><span> u8 revid = pci_read_config8(dev, 0x8);</span><br><span> </span><br><span> switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index ed7e2fa..31b1b78 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -45,7 +45,7 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_core_init(device_t cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_core_init(struct device *cpu)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(cpu));</span><br><span>@@ -215,7 +215,7 @@</span><br><span> .post_mp_init = southcluster_smm_enable_smi,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void soc_init_cpus(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_init_cpus(struct device *dev)</span><br><span> {</span><br><span> struct bus *cpu_bus = dev->link_list;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c</span><br><span>index 9057953..44116a8 100644</span><br><span>--- a/src/soc/intel/braswell/emmc.c</span><br><span>+++ b/src/soc/intel/braswell/emmc.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> REG_SCRIPT_END,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void emmc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void emmc_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c</span><br><span>index 8481446..40bdf83 100644</span><br><span>--- a/src/soc/intel/braswell/gfx.c</span><br><span>+++ b/src/soc/intel/braswell/gfx.c</span><br><span>@@ -41,12 +41,12 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)</span><br><span> {</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_pre_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_pre_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -54,7 +54,7 @@</span><br><span> gfx_run_script(dev, gpu_pre_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_post_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_post_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -62,7 +62,7 @@</span><br><span> gfx_run_script(dev, gfx_post_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h</span><br><span>index 7f57727..162f81a 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/acpi.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/acpi.h</span><br><span>@@ -24,8 +24,8 @@</span><br><span> void acpi_fill_in_fadt(acpi_fadt_t *fadt);</span><br><span> unsigned long acpi_madt_irq_overrides(unsigned long current);</span><br><span> void acpi_init_gnvs(global_nvs_t *gnvs);</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_inject_dsdt(device_t device);</span><br><span style="color: hsl(0, 100%, 40%);">-unsigned long southcluster_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_inject_dsdt(struct device *device);</span><br><span style="color: hsl(120, 100%, 40%);">+unsigned long southcluster_write_acpi_tables(struct device *device,</span><br><span> unsigned long current, struct acpi_rsdp *rsdp);</span><br><span> </span><br><span> #endif /* _SOC_ACPI_H_ */</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h</span><br><span>index 3f8249b..d735de5 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/ramstage.h</span><br><span>@@ -96,10 +96,10 @@</span><br><span> * initialization, but it's after console and cbmem has been reinitialized.</span><br><span> */</span><br><span> void soc_init_pre_device(struct soc_intel_braswell_config *config);</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_init_cpus(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_init_cpus(struct device *dev);</span><br><span> void set_max_freq(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);</span><br><span> int SocStepping(void);</span><br><span> void board_silicon_USB2_override(SILICON_INIT_UPD *params);</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c</span><br><span>index 436099b..f8660bc 100644</span><br><span>--- a/src/soc/intel/braswell/lpe.c</span><br><span>+++ b/src/soc/intel/braswell/lpe.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> #define FIRMWARE_REG_BASE_C0 0x144000</span><br><span> #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void assign_device_nvs(device_t dev, u32 *field, unsigned int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -53,7 +53,7 @@</span><br><span> *field = res->base;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_enable_acpi_mode(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_enable_acpi_mode(struct device *dev)</span><br><span> {</span><br><span> static const struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -87,7 +87,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void setup_codec_clock(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_codec_clock(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> u32 *clk_reg;</span><br><span>@@ -123,7 +123,7 @@</span><br><span> write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_stash_firmware_info(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_stash_firmware_info(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct resource *mmio;</span><br><span>@@ -148,7 +148,7 @@</span><br><span> }</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span>@@ -162,7 +162,7 @@</span><br><span> lpe_enable_acpi_mode(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> pci_dev_read_resources(dev);</span><br><span>@@ -184,7 +184,7 @@</span><br><span> FIRMWARE_PHYS_LENGTH >> 10);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_set_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c</span><br><span>index cbef92e..9248d82 100644</span><br><span>--- a/src/soc/intel/braswell/lpss.c</span><br><span>+++ b/src/soc/intel/braswell/lpss.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> </span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -67,7 +67,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)</span><br><span> {</span><br><span> *iosf_reg = -1;</span><br><span> *nvs_index = -1;</span><br><span>@@ -110,7 +110,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i2c_disable_resets(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i2c_disable_resets(struct device *dev)</span><br><span> {</span><br><span> /* Release the I2C devices from reset. */</span><br><span> static const struct reg_script ops[] = {</span><br><span>@@ -137,7 +137,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpss_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpss_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> int iosf_reg, nvs_index;</span><br><span>diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c</span><br><span>index dc72a46..3245a28 100644</span><br><span>--- a/src/soc/intel/braswell/northcluster.c</span><br><span>+++ b/src/soc/intel/braswell/northcluster.c</span><br><span>@@ -81,7 +81,7 @@</span><br><span> return tolm;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void nc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void nc_read_resources(struct device *dev)</span><br><span> {</span><br><span> unsigned long mmconf;</span><br><span> unsigned long bmbound_k;</span><br><span>diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c</span><br><span>index 9ea154a..1a127f4 100644</span><br><span>--- a/src/soc/intel/braswell/pcie.c</span><br><span>+++ b/src/soc/intel/braswell/pcie.c</span><br><span>@@ -29,17 +29,17 @@</span><br><span> static int pll_en_off;</span><br><span> static uint32_t strpfusecfg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_offset(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_offset(struct device *dev)</span><br><span> {</span><br><span> return PCI_FUNC(dev->path.pci.devfn);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int is_first_port(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int is_first_port(struct device *dev)</span><br><span> {</span><br><span> return root_port_offset(dev) == PCIE_PORT1_FUNC;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -52,7 +52,7 @@</span><br><span> REG_SCRIPT_END,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void check_port_enabled(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void check_port_enabled(struct device *dev)</span><br><span> {</span><br><span> int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;</span><br><span> </span><br><span>@@ -81,10 +81,10 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void check_device_present(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void check_device_present(struct device *dev)</span><br><span> {</span><br><span> /* port1_dev will store the dev struct pointer of the PORT1 */</span><br><span style="color: hsl(0, 100%, 40%);">- static device_t port1_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ static struct device *port1_dev;</span><br><span> </span><br><span> /*</span><br><span> * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW.</span><br><span>@@ -135,7 +135,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_enable(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -159,7 +159,7 @@</span><br><span> southcluster_enable_dev(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_root_set_subsystem(device_t dev, unsigned int vid,</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_root_set_subsystem(struct device *dev, unsigned int vid,</span><br><span> unsigned int did)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",</span><br><span>diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c</span><br><span>index 1b71f92..3ab1af3 100644</span><br><span>--- a/src/soc/intel/braswell/ramstage.c</span><br><span>+++ b/src/soc/intel/braswell/ramstage.c</span><br><span>@@ -78,7 +78,7 @@</span><br><span> </span><br><span> static void fill_in_pattrs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> msr_t msr;</span><br><span> struct pattrs *attrs = (struct pattrs *)pattrs_get();</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c</span><br><span>index 42699f8..8052b29 100644</span><br><span>--- a/src/soc/intel/braswell/sata.c</span><br><span>+++ b/src/soc/intel/braswell/sata.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> southcluster_enable_dev(dev);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c</span><br><span>index 6538c5c..122c67e 100644</span><br><span>--- a/src/soc/intel/braswell/scc.c</span><br><span>+++ b/src/soc/intel/braswell/scc.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #include <soc/nvs.h></span><br><span> #include <soc/ramstage.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)</span><br><span> {</span><br><span> struct resource *bar;</span><br><span> global_nvs_t *gnvs;</span><br><span>diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c</span><br><span>index 4f192ab..97c39b3 100644</span><br><span>--- a/src/soc/intel/braswell/sd.c</span><br><span>+++ b/src/soc/intel/braswell/sd.c</span><br><span>@@ -31,7 +31,7 @@</span><br><span> #define CAP_OVERRIDE_HIGH 0xa4</span><br><span> # define USE_CAP_OVERRIDES (1 << 31)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sd_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sd_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c</span><br><span>index 0f5c7c9..3c85b6d 100644</span><br><span>--- a/src/soc/intel/braswell/smihandler.c</span><br><span>+++ b/src/soc/intel/braswell/smihandler.c</span><br><span>@@ -70,7 +70,7 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c</span><br><span>index 05fa855..85bb4af 100644</span><br><span>--- a/src/soc/intel/braswell/southcluster.c</span><br><span>+++ b/src/soc/intel/braswell/southcluster.c</span><br><span>@@ -53,14 +53,14 @@</span><br><span> }</span><br><span> </span><br><span> static inline void</span><br><span style="color: hsl(0, 100%, 40%);">-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)</span><br><span style="color: hsl(120, 100%, 40%);">+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n",</span><br><span> __FILE__, __func__, dev_name(dev), addr, size);</span><br><span> mmio_resource(dev, i, addr >> 10, size >> 10);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -97,7 +97,7 @@</span><br><span> * Note: this function assumes there is no overlap with the default LPC device's</span><br><span> * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resource(device_t dev, int base, int size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resource(struct device *dev, int base, int size, int index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -113,7 +113,7 @@</span><br><span> res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -133,7 +133,7 @@</span><br><span> sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_read_resources(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_SPEW, "%s/%s ( %s )\n",</span><br><span> __FILE__, __func__, dev_name(dev));</span><br><span>@@ -154,7 +154,7 @@</span><br><span> cmos_init(rtc_failure());</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_init(struct device *dev)</span><br><span> {</span><br><span> int i;</span><br><span> const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;</span><br><span>@@ -198,7 +198,7 @@</span><br><span> */</span><br><span> </span><br><span> /* Set bit in function disble register to hide this device. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_disable_devfn(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_disable_devfn(struct device *dev)</span><br><span> {</span><br><span> void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);</span><br><span> void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);</span><br><span>@@ -287,7 +287,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_d3hot_bits(device_t dev, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_d3hot_bits(struct device *dev, int offset)</span><br><span> {</span><br><span> uint32_t reg8;</span><br><span> </span><br><span>@@ -304,7 +304,7 @@</span><br><span> * cannot put HDA into D3Hot. Instead perform this workaround to make some of</span><br><span> * the audio paths work for LPE audio.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void hda_work_around(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hda_work_around(struct device *dev)</span><br><span> {</span><br><span> void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);</span><br><span> </span><br><span>@@ -326,7 +326,7 @@</span><br><span> pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int place_device_in_d3hot(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int place_device_in_d3hot(struct device *dev)</span><br><span> {</span><br><span> unsigned int offset;</span><br><span> </span><br><span>@@ -405,7 +405,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Common PCI device function disable. */</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span> </span><br><span>diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c</span><br><span>index b9e1627..3bf83d9 100644</span><br><span>--- a/src/soc/intel/braswell/spi.c</span><br><span>+++ b/src/soc/intel/braswell/spi.c</span><br><span>@@ -233,7 +233,7 @@</span><br><span> </span><br><span> static ich9_spi_regs *spi_regs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> uint32_t sbase;</span><br><span> </span><br><span> #if ENV_SMM</span><br><span>diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c</span><br><span>index 76319c0..49b6c4b 100644</span><br><span>--- a/src/soc/intel/braswell/xhci.c</span><br><span>+++ b/src/soc/intel/braswell/xhci.c</span><br><span>@@ -32,7 +32,7 @@</span><br><span> </span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void xhci_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_braswell_config *config = dev->chip_info;</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26457">change 26457</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26457"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793 </div>
<div style="display:none"> Gerrit-Change-Number: 26457 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>