[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue May 22 10:45:33 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26456
Change subject: soc/intel/baytrail: Get rid of device_t
......................................................................
soc/intel/baytrail: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/soc/intel/baytrail/acpi.c
M src/soc/intel/baytrail/chip.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/include/soc/ramstage.h
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/ramstage.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/scc.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/baytrail/xhci.c
20 files changed, 64 insertions(+), 64 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/26456/1
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index b3f5ea6..31435f7 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -443,7 +443,7 @@
acpigen_pop_len();
}
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index dab2cd1..b898dc9 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -22,7 +22,7 @@
#include <soc/ramstage.h>
#include "chip.h"
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@@ -44,7 +44,7 @@
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
@@ -72,7 +72,7 @@
.init = soc_init,
};
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index ed18ce1..77d2dda 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -44,7 +44,7 @@
REG_SCRIPT_END
};
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init BayTrail core.\n");
@@ -199,7 +199,7 @@
.post_mp_init = southcluster_smm_enable_smi,
};
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 97d4b4b..e2ff318 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -87,7 +87,7 @@
REG_SCRIPT_END
};
-static void usb2_phy_init(device_t dev)
+static void usb2_phy_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
@@ -122,7 +122,7 @@
reg_script_run(usb2_phy_script);
}
-static void ehci_init(device_t dev)
+static void ehci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script ehci_hc_init[] = {
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index b2a30dc..6dd8f70 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -45,7 +45,7 @@
REG_SCRIPT_END,
};
-static void emmc_init(device_t dev)
+static void emmc_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 45bcd7b..06ef1a4 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -38,7 +38,7 @@
* Lock Power Context Base Register to point to a 24KB block
* of memory in GSM. Power context save data is stored here.
*/
-static void gfx_lock_pcbase(device_t dev)
+static void gfx_lock_pcbase(struct device *dev)
{
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
@@ -263,18 +263,18 @@
REG_SCRIPT_END
};
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
{
reg_script_run_on_dev(dev, ops);
}
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
}
-static void gfx_pm_init(device_t dev)
+static void gfx_pm_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Power Management Init\n");
gfx_run_script(dev, gfx_init_script);
@@ -283,13 +283,13 @@
gfx_lock_pcbase(dev);
}
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
{
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
}
-static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
+static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz)
{
int divider;
struct resource *res;
@@ -310,7 +310,7 @@
write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
}
-static void gfx_panel_setup(device_t dev)
+static void gfx_panel_setup(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script gfx_pipea_init[] = {
@@ -378,7 +378,7 @@
gnvs_ptr->aslb = aslb;
}
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
{
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c
index 172ee38..ec40868 100644
--- a/src/soc/intel/baytrail/hda.c
+++ b/src/soc/intel/baytrail/hda.c
@@ -69,7 +69,7 @@
0x20671f58,
};
-static void hda_init(device_t dev)
+static void hda_init(struct device *dev)
{
struct resource *res;
int codec_mask;
diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h
index 083bf77..827c706 100644
--- a/src/soc/intel/baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/baytrail/include/soc/ramstage.h
@@ -22,16 +22,16 @@
/* The baytrail_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
+void southcluster_enable_dev(struct device *dev);
#if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)
void baytrail_run_reference_code(void);
#else
static inline void baytrail_run_reference_code(void) {}
#endif
void baytrail_init_scc(void);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 41cc090..2830f00 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -41,7 +41,7 @@
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
{
struct resource *res;
@@ -50,7 +50,7 @@
*field = res->base;
}
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -83,7 +83,7 @@
reg_script_run_on_dev(dev, ops);
}
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
{
uint32_t reg;
u32 *clk_reg;
@@ -121,7 +121,7 @@
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
{
struct resource *res;
struct resource *mmio;
@@ -147,7 +147,7 @@
}
}
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -159,7 +159,7 @@
lpe_enable_acpi_mode(dev);
}
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index c29d721..1af475e 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -29,7 +29,7 @@
#include "chip.h"
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -66,7 +66,7 @@
reg_script_run_on_dev(dev, ops);
}
-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
{
struct reg_script ops[] = {
REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
@@ -78,7 +78,7 @@
reg_script_run_on_dev(dev, ops);
}
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
{
*iosf_reg = -1;
*nvs_index = -1;
@@ -119,7 +119,7 @@
}
}
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
{
/* Release the I2C devices from reset. */
static const struct reg_script ops[] = {
@@ -146,7 +146,7 @@
}
}
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
int iosf_reg, nvs_index;
diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c
index c8ba9c1..8186cec 100644
--- a/src/soc/intel/baytrail/northcluster.c
+++ b/src/soc/intel/baytrail/northcluster.c
@@ -75,7 +75,7 @@
return tolm;
}
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
{
unsigned long mmconf;
unsigned long bmbound;
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index b5d18a0..39e0918 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -30,12 +30,12 @@
static int pll_en_off;
static uint32_t strpfusecfg;
-static inline int root_port_offset(device_t dev)
+static inline int root_port_offset(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
-static inline int is_first_port(device_t dev)
+static inline int is_first_port(struct device *dev)
{
return root_port_offset(dev) == PCIE_PORT1_FUNC;
}
@@ -84,7 +84,7 @@
REG_SCRIPT_END,
};
-static void byt_pcie_init(device_t dev)
+static void byt_pcie_init(struct device *dev)
{
struct reg_script init_script[] = {
REG_SCRIPT_NEXT(init_static_before_exit_latency),
@@ -125,7 +125,7 @@
REG_SCRIPT_END,
};
-static void check_port_enabled(device_t dev)
+static void check_port_enabled(struct device *dev)
{
int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;
@@ -151,7 +151,7 @@
}
}
-static u8 all_ports_no_dev_present(device_t dev)
+static u8 all_ports_no_dev_present(struct device *dev)
{
u8 func;
u8 temp = dev->path.pci.devfn;
@@ -180,7 +180,7 @@
return device_not_present;
}
-static void check_device_present(device_t dev)
+static void check_device_present(struct device *dev)
{
/* Set slot implemented. */
pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);
@@ -204,7 +204,7 @@
}
}
-static void byt_pcie_enable(device_t dev)
+static void byt_pcie_enable(struct device *dev)
{
if (is_first_port(dev)) {
struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -226,7 +226,7 @@
southcluster_enable_dev(dev);
}
-static void byt_pciexp_scan_bridge(device_t dev)
+static void byt_pciexp_scan_bridge(struct device *dev)
{
static const struct reg_script wait_for_link_active[] = {
REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000),
@@ -239,7 +239,7 @@
do_pci_scan_bridge(dev, pciexp_scan_bus);
}
-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)
+static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did)
{
uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index c0cdd23..486f5a3 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -75,7 +75,7 @@
static void fill_in_pattrs(void)
{
- device_t dev;
+ struct device *dev;
msr_t msr;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 12484be..4724d55 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -155,7 +155,7 @@
pci_write_config32(dev, 0x98, reg32);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
config_t *config = dev->chip_info;
u8 reg8;
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 27edae1..7f97f09 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -83,7 +83,7 @@
reg_script_run(scc_after_dll);
}
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index 8d0c14e..0c03e56 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -30,7 +30,7 @@
#define CAP_OVERRIDE_HIGH 0xa4
# define USE_CAP_OVERRIDES (1 << 31)
-static void sd_init(device_t dev)
+static void sd_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 683bf30..6773bce 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -69,7 +69,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 84ae0ee..cc78339 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -42,12 +42,12 @@
#include <cpu/cpu.h>
static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
@@ -82,7 +82,7 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -95,7 +95,7 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
@@ -112,7 +112,7 @@
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
}
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -137,7 +137,7 @@
* or configuration. This is definitely a hack, but it helps the kernel
* along.
*/
-static void com1_configure_resume(device_t dev)
+static void com1_configure_resume(struct device *dev)
{
const uint16_t port = 0x3f8;
@@ -165,7 +165,7 @@
outb(3, port + UART8250_LCR);
}
-static void sc_init(device_t dev)
+static void sc_init(struct device *dev)
{
int i;
u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
@@ -207,7 +207,7 @@
*/
/* Set bit in function disable register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
{
u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
@@ -316,7 +316,7 @@
}
}
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
{
uint32_t reg8;
printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -328,7 +328,7 @@
/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
* cannot put HDA into D3Hot. Instead perform this workaround to make some of
* the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
{
u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
@@ -345,7 +345,7 @@
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
}
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
{
unsigned offset;
@@ -461,7 +461,7 @@
}
/* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
@@ -494,7 +494,7 @@
}
}
-static void southcluster_inject_dsdt(device_t device)
+static void southcluster_inject_dsdt(struct device *device)
{
global_nvs_t *gnvs;
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 918e6d6..f4fe112 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -264,7 +264,7 @@
static ich9_spi_regs *spi_regs(void)
{
- device_t dev;
+ struct device *dev;
uint32_t sbase;
#ifdef __SMM__
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 350c629..6ad63ba 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -146,7 +146,7 @@
};
/* Warm Reset a USB3 port */
-static void xhci_reset_port_usb3(device_t dev, int port)
+static void xhci_reset_port_usb3(struct device *dev, int port)
{
struct reg_script reset_port_usb3_script[] = {
/* Issue Warm Port Rest to the port */
@@ -165,7 +165,7 @@
}
/* Prepare ports to be routed to EHCI or XHCI */
-static void xhci_route_all(device_t dev)
+static void xhci_route_all(struct device *dev)
{
static const struct reg_script xhci_route_all_script[] = {
/* USB3 SuperSpeed Enable */
@@ -194,7 +194,7 @@
}
}
-static void xhci_init(device_t dev)
+static void xhci_init(struct device *dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script xhci_hc_init[] = {
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e
Gerrit-Change-Number: 26456
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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