<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26456">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/baytrail: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/soc/intel/baytrail/acpi.c<br>M src/soc/intel/baytrail/chip.c<br>M src/soc/intel/baytrail/cpu.c<br>M src/soc/intel/baytrail/ehci.c<br>M src/soc/intel/baytrail/emmc.c<br>M src/soc/intel/baytrail/gfx.c<br>M src/soc/intel/baytrail/hda.c<br>M src/soc/intel/baytrail/include/soc/ramstage.h<br>M src/soc/intel/baytrail/lpe.c<br>M src/soc/intel/baytrail/lpss.c<br>M src/soc/intel/baytrail/northcluster.c<br>M src/soc/intel/baytrail/pcie.c<br>M src/soc/intel/baytrail/ramstage.c<br>M src/soc/intel/baytrail/sata.c<br>M src/soc/intel/baytrail/scc.c<br>M src/soc/intel/baytrail/sd.c<br>M src/soc/intel/baytrail/smihandler.c<br>M src/soc/intel/baytrail/southcluster.c<br>M src/soc/intel/baytrail/spi.c<br>M src/soc/intel/baytrail/xhci.c<br>20 files changed, 64 insertions(+), 64 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/26456/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c</span><br><span>index b3f5ea6..31435f7 100644</span><br><span>--- a/src/soc/intel/baytrail/acpi.c</span><br><span>+++ b/src/soc/intel/baytrail/acpi.c</span><br><span>@@ -443,7 +443,7 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void generate_cpu_entries(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+void generate_cpu_entries(struct device *device)</span><br><span> {</span><br><span> int core;</span><br><span> int pcontrol_blk = get_pmbase(), plen = 6;</span><br><span>diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c</span><br><span>index dab2cd1..b898dc9 100644</span><br><span>--- a/src/soc/intel/baytrail/chip.c</span><br><span>+++ b/src/soc/intel/baytrail/chip.c</span><br><span>@@ -22,7 +22,7 @@</span><br><span> #include <soc/ramstage.h></span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_domain_set_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_domain_set_resources(struct device *dev)</span><br><span> {</span><br><span> assign_resources(dev->link_list);</span><br><span> }</span><br><span>@@ -44,7 +44,7 @@</span><br><span> };</span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_dev(struct device *dev)</span><br><span> {</span><br><span> /* Set the operations if it is a special bus type */</span><br><span> if (dev->path.type == DEVICE_PATH_DOMAIN) {</span><br><span>@@ -72,7 +72,7 @@</span><br><span> .init = soc_init,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c</span><br><span>index ed18ce1..77d2dda 100644</span><br><span>--- a/src/soc/intel/baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/baytrail/cpu.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void baytrail_core_init(device_t cpu)</span><br><span style="color: hsl(120, 100%, 40%);">+static void baytrail_core_init(struct device *cpu)</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "Init BayTrail core.\n");</span><br><span> </span><br><span>@@ -199,7 +199,7 @@</span><br><span> .post_mp_init = southcluster_smm_enable_smi,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void baytrail_init_cpus(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void baytrail_init_cpus(struct device *dev)</span><br><span> {</span><br><span> struct bus *cpu_bus = dev->link_list;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c</span><br><span>index 97d4b4b..e2ff318 100644</span><br><span>--- a/src/soc/intel/baytrail/ehci.c</span><br><span>+++ b/src/soc/intel/baytrail/ehci.c</span><br><span>@@ -87,7 +87,7 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb2_phy_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb2_phy_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?</span><br><span>@@ -122,7 +122,7 @@</span><br><span> reg_script_run(usb2_phy_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void ehci_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void ehci_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> struct reg_script ehci_hc_init[] = {</span><br><span>diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c</span><br><span>index b2a30dc..6dd8f70 100644</span><br><span>--- a/src/soc/intel/baytrail/emmc.c</span><br><span>+++ b/src/soc/intel/baytrail/emmc.c</span><br><span>@@ -45,7 +45,7 @@</span><br><span> REG_SCRIPT_END,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void emmc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void emmc_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c</span><br><span>index 45bcd7b..06ef1a4 100644</span><br><span>--- a/src/soc/intel/baytrail/gfx.c</span><br><span>+++ b/src/soc/intel/baytrail/gfx.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> * Lock Power Context Base Register to point to a 24KB block</span><br><span> * of memory in GSM. Power context save data is stored here.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_lock_pcbase(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_lock_pcbase(struct device *dev)</span><br><span> {</span><br><span> struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);</span><br><span> const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,</span><br><span>@@ -263,18 +263,18 @@</span><br><span> REG_SCRIPT_END</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)</span><br><span> {</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_pre_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_pre_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");</span><br><span> gfx_run_script(dev, gpu_pre_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_pm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_pm_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_INFO, "GFX: Power Management Init\n");</span><br><span> gfx_run_script(dev, gfx_init_script);</span><br><span>@@ -283,13 +283,13 @@</span><br><span> gfx_lock_pcbase(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_post_vbios_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_post_vbios_init(struct device *dev)</span><br><span> {</span><br><span> printk(BIOS_INFO, "GFX: Post VBIOS Init\n");</span><br><span> gfx_run_script(dev, gfx_post_vbios_script);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz)</span><br><span> {</span><br><span> int divider;</span><br><span> struct resource *res;</span><br><span>@@ -310,7 +310,7 @@</span><br><span> write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_panel_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_panel_setup(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> struct reg_script gfx_pipea_init[] = {</span><br><span>@@ -378,7 +378,7 @@</span><br><span> gnvs_ptr->aslb = aslb;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void gfx_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void gfx_init(struct device *dev)</span><br><span> {</span><br><span> /* Pre VBIOS Init */</span><br><span> gfx_pre_vbios_init(dev);</span><br><span>diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c</span><br><span>index 172ee38..ec40868 100644</span><br><span>--- a/src/soc/intel/baytrail/hda.c</span><br><span>+++ b/src/soc/intel/baytrail/hda.c</span><br><span>@@ -69,7 +69,7 @@</span><br><span> 0x20671f58,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void hda_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hda_init(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> int codec_mask;</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/ramstage.h b/src/soc/intel/baytrail/include/soc/ramstage.h</span><br><span>index 083bf77..827c706 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/ramstage.h</span><br><span>@@ -22,16 +22,16 @@</span><br><span> /* The baytrail_init_pre_device() function is called prior to device</span><br><span> * initialization, but it's after console and cbmem has been reinitialized. */</span><br><span> void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);</span><br><span style="color: hsl(0, 100%, 40%);">-void baytrail_init_cpus(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void baytrail_init_cpus(struct device *dev);</span><br><span> void set_max_freq(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev);</span><br><span> #if IS_ENABLED(CONFIG_HAVE_REFCODE_BLOB)</span><br><span> void baytrail_run_reference_code(void);</span><br><span> #else</span><br><span> static inline void baytrail_run_reference_code(void) {}</span><br><span> #endif</span><br><span> void baytrail_init_scc(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);</span><br><span style="color: hsl(120, 100%, 40%);">+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);</span><br><span> </span><br><span> extern struct pci_operations soc_pci_ops;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c</span><br><span>index 41cc090..2830f00 100644</span><br><span>--- a/src/soc/intel/baytrail/lpe.c</span><br><span>+++ b/src/soc/intel/baytrail/lpe.c</span><br><span>@@ -41,7 +41,7 @@</span><br><span> #define FIRMWARE_REG_BASE_C0 0x144000</span><br><span> #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -50,7 +50,7 @@</span><br><span> *field = res->base;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_enable_acpi_mode(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_enable_acpi_mode(struct device *dev)</span><br><span> {</span><br><span> static const struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -83,7 +83,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void setup_codec_clock(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_codec_clock(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg;</span><br><span> u32 *clk_reg;</span><br><span>@@ -121,7 +121,7 @@</span><br><span> write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_stash_firmware_info(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_stash_firmware_info(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct resource *mmio;</span><br><span>@@ -147,7 +147,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> </span><br><span>@@ -159,7 +159,7 @@</span><br><span> lpe_enable_acpi_mode(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpe_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpe_read_resources(struct device *dev)</span><br><span> {</span><br><span> pci_dev_read_resources(dev);</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c</span><br><span>index c29d721..1af475e 100644</span><br><span>--- a/src/soc/intel/baytrail/lpss.c</span><br><span>+++ b/src/soc/intel/baytrail/lpss.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> #include "chip.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>@@ -66,7 +66,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,</span><br><span>@@ -78,7 +78,7 @@</span><br><span> reg_script_run_on_dev(dev, ops);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)</span><br><span> {</span><br><span> *iosf_reg = -1;</span><br><span> *nvs_index = -1;</span><br><span>@@ -119,7 +119,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void i2c_disable_resets(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void i2c_disable_resets(struct device *dev)</span><br><span> {</span><br><span> /* Release the I2C devices from reset. */</span><br><span> static const struct reg_script ops[] = {</span><br><span>@@ -146,7 +146,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpss_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpss_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> int iosf_reg, nvs_index;</span><br><span>diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c</span><br><span>index c8ba9c1..8186cec 100644</span><br><span>--- a/src/soc/intel/baytrail/northcluster.c</span><br><span>+++ b/src/soc/intel/baytrail/northcluster.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> return tolm;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void nc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void nc_read_resources(struct device *dev)</span><br><span> {</span><br><span> unsigned long mmconf;</span><br><span> unsigned long bmbound;</span><br><span>diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c</span><br><span>index b5d18a0..39e0918 100644</span><br><span>--- a/src/soc/intel/baytrail/pcie.c</span><br><span>+++ b/src/soc/intel/baytrail/pcie.c</span><br><span>@@ -30,12 +30,12 @@</span><br><span> static int pll_en_off;</span><br><span> static uint32_t strpfusecfg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_offset(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_offset(struct device *dev)</span><br><span> {</span><br><span> return PCI_FUNC(dev->path.pci.devfn);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int is_first_port(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int is_first_port(struct device *dev)</span><br><span> {</span><br><span> return root_port_offset(dev) == PCIE_PORT1_FUNC;</span><br><span> }</span><br><span>@@ -84,7 +84,7 @@</span><br><span> REG_SCRIPT_END,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void byt_pcie_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void byt_pcie_init(struct device *dev)</span><br><span> {</span><br><span> struct reg_script init_script[] = {</span><br><span> REG_SCRIPT_NEXT(init_static_before_exit_latency),</span><br><span>@@ -125,7 +125,7 @@</span><br><span> REG_SCRIPT_END,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void check_port_enabled(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void check_port_enabled(struct device *dev)</span><br><span> {</span><br><span> int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT;</span><br><span> </span><br><span>@@ -151,7 +151,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u8 all_ports_no_dev_present(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 all_ports_no_dev_present(struct device *dev)</span><br><span> {</span><br><span> u8 func;</span><br><span> u8 temp = dev->path.pci.devfn;</span><br><span>@@ -180,7 +180,7 @@</span><br><span> return device_not_present;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void check_device_present(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void check_device_present(struct device *dev)</span><br><span> {</span><br><span> /* Set slot implemented. */</span><br><span> pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI);</span><br><span>@@ -204,7 +204,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void byt_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void byt_pcie_enable(struct device *dev)</span><br><span> {</span><br><span> if (is_first_port(dev)) {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span>@@ -226,7 +226,7 @@</span><br><span> southcluster_enable_dev(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void byt_pciexp_scan_bridge(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void byt_pciexp_scan_bridge(struct device *dev)</span><br><span> {</span><br><span> static const struct reg_script wait_for_link_active[] = {</span><br><span> REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000),</span><br><span>@@ -239,7 +239,7 @@</span><br><span> do_pci_scan_bridge(dev, pciexp_scan_bus);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did)</span><br><span> {</span><br><span> uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff);</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c</span><br><span>index c0cdd23..486f5a3 100644</span><br><span>--- a/src/soc/intel/baytrail/ramstage.c</span><br><span>+++ b/src/soc/intel/baytrail/ramstage.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span> </span><br><span> static void fill_in_pattrs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> msr_t msr;</span><br><span> struct pattrs *attrs = (struct pattrs *)pattrs_get();</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c</span><br><span>index 12484be..4724d55 100644</span><br><span>--- a/src/soc/intel/baytrail/sata.c</span><br><span>+++ b/src/soc/intel/baytrail/sata.c</span><br><span>@@ -155,7 +155,7 @@</span><br><span> pci_write_config32(dev, 0x98, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> config_t *config = dev->chip_info;</span><br><span> u8 reg8;</span><br><span>diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c</span><br><span>index 27edae1..7f97f09 100644</span><br><span>--- a/src/soc/intel/baytrail/scc.c</span><br><span>+++ b/src/soc/intel/baytrail/scc.c</span><br><span>@@ -83,7 +83,7 @@</span><br><span> reg_script_run(scc_after_dll);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)</span><br><span style="color: hsl(120, 100%, 40%);">+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)</span><br><span> {</span><br><span> struct reg_script ops[] = {</span><br><span> /* Disable PCI interrupt, enable Memory and Bus Master */</span><br><span>diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c</span><br><span>index 8d0c14e..0c03e56 100644</span><br><span>--- a/src/soc/intel/baytrail/sd.c</span><br><span>+++ b/src/soc/intel/baytrail/sd.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> #define CAP_OVERRIDE_HIGH 0xa4</span><br><span> # define USE_CAP_OVERRIDES (1 << 31)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sd_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sd_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c</span><br><span>index 683bf30..6773bce 100644</span><br><span>--- a/src/soc/intel/baytrail/smihandler.c</span><br><span>+++ b/src/soc/intel/baytrail/smihandler.c</span><br><span>@@ -69,7 +69,7 @@</span><br><span> for (slot = 0; slot < 0x20; slot++) {</span><br><span> for (func = 0; func < 8; func++) {</span><br><span> u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span> val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c</span><br><span>index 84ae0ee..cc78339 100644</span><br><span>--- a/src/soc/intel/baytrail/southcluster.c</span><br><span>+++ b/src/soc/intel/baytrail/southcluster.c</span><br><span>@@ -42,12 +42,12 @@</span><br><span> #include <cpu/cpu.h></span><br><span> </span><br><span> static inline void</span><br><span style="color: hsl(0, 100%, 40%);">-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)</span><br><span style="color: hsl(120, 100%, 40%);">+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)</span><br><span> {</span><br><span> mmio_resource(dev, i, addr >> 10, size >> 10);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span> add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);</span><br><span> add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);</span><br><span>@@ -82,7 +82,7 @@</span><br><span> * Note: this function assumes there is no overlap with the default LPC device's</span><br><span> * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resource(device_t dev, int base, int size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resource(struct device *dev, int base, int size, int index)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -95,7 +95,7 @@</span><br><span> res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>@@ -112,7 +112,7 @@</span><br><span> sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_read_resources(struct device *dev)</span><br><span> {</span><br><span> /* Get the normal PCI resources of this device. */</span><br><span> pci_dev_read_resources(dev);</span><br><span>@@ -137,7 +137,7 @@</span><br><span> * or configuration. This is definitely a hack, but it helps the kernel</span><br><span> * along.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void com1_configure_resume(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void com1_configure_resume(struct device *dev)</span><br><span> {</span><br><span> const uint16_t port = 0x3f8;</span><br><span> </span><br><span>@@ -165,7 +165,7 @@</span><br><span> outb(3, port + UART8250_LCR);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_init(struct device *dev)</span><br><span> {</span><br><span> int i;</span><br><span> u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);</span><br><span>@@ -207,7 +207,7 @@</span><br><span> */</span><br><span> </span><br><span> /* Set bit in function disable register to hide this device. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sc_disable_devfn(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sc_disable_devfn(struct device *dev)</span><br><span> {</span><br><span> u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);</span><br><span> u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);</span><br><span>@@ -316,7 +316,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void set_d3hot_bits(device_t dev, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void set_d3hot_bits(struct device *dev, int offset)</span><br><span> {</span><br><span> uint32_t reg8;</span><br><span> printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);</span><br><span>@@ -328,7 +328,7 @@</span><br><span> /* Parts of the audio subsystem are powered by the HDA device. Therefore, one</span><br><span> * cannot put HDA into D3Hot. Instead perform this workaround to make some of</span><br><span> * the audio paths work for LPE audio. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void hda_work_around(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void hda_work_around(struct device *dev)</span><br><span> {</span><br><span> u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);</span><br><span> </span><br><span>@@ -345,7 +345,7 @@</span><br><span> pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int place_device_in_d3hot(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int place_device_in_d3hot(struct device *dev)</span><br><span> {</span><br><span> unsigned offset;</span><br><span> </span><br><span>@@ -461,7 +461,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Common PCI device function disable. */</span><br><span style="color: hsl(0, 100%, 40%);">-void southcluster_enable_dev(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void southcluster_enable_dev(struct device *dev)</span><br><span> {</span><br><span> uint32_t reg32;</span><br><span> </span><br><span>@@ -494,7 +494,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southcluster_inject_dsdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southcluster_inject_dsdt(struct device *device)</span><br><span> {</span><br><span> global_nvs_t *gnvs;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c</span><br><span>index 918e6d6..f4fe112 100644</span><br><span>--- a/src/soc/intel/baytrail/spi.c</span><br><span>+++ b/src/soc/intel/baytrail/spi.c</span><br><span>@@ -264,7 +264,7 @@</span><br><span> </span><br><span> static ich9_spi_regs *spi_regs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> uint32_t sbase;</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span>diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c</span><br><span>index 350c629..6ad63ba 100644</span><br><span>--- a/src/soc/intel/baytrail/xhci.c</span><br><span>+++ b/src/soc/intel/baytrail/xhci.c</span><br><span>@@ -146,7 +146,7 @@</span><br><span> };</span><br><span> </span><br><span> /* Warm Reset a USB3 port */</span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_reset_port_usb3(device_t dev, int port)</span><br><span style="color: hsl(120, 100%, 40%);">+static void xhci_reset_port_usb3(struct device *dev, int port)</span><br><span> {</span><br><span> struct reg_script reset_port_usb3_script[] = {</span><br><span> /* Issue Warm Port Rest to the port */</span><br><span>@@ -165,7 +165,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ports to be routed to EHCI or XHCI */</span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_route_all(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void xhci_route_all(struct device *dev)</span><br><span> {</span><br><span> static const struct reg_script xhci_route_all_script[] = {</span><br><span> /* USB3 SuperSpeed Enable */</span><br><span>@@ -194,7 +194,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void xhci_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void xhci_init(struct device *dev)</span><br><span> {</span><br><span> struct soc_intel_baytrail_config *config = dev->chip_info;</span><br><span> struct reg_script xhci_hc_init[] = {</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26456">change 26456</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26456"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e </div>
<div style="display:none"> Gerrit-Change-Number: 26456 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>