[coreboot-gerrit] Change in coreboot[master]: src: Remove non-ascii characters
Martin Roth (Code Review)
gerrit at coreboot.org
Mon May 21 01:48:59 CEST 2018
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/26434
Change subject: src: Remove non-ascii characters
......................................................................
src: Remove non-ascii characters
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/drivers/i2c/max98373/chip.h
M src/drivers/i2c/max98927/chip.h
M src/soc/intel/apollolake/include/soc/meminit.h
M src/soc/intel/cannonlake/lockdown.c
M src/soc/intel/skylake/lockdown.c
M src/soc/rockchip/rk3399/Kconfig
M src/soc/rockchip/rk3399/clock.c
M src/southbridge/via/vt8237r/acpi/default_irq_route.asl
8 files changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/26434/1
diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h
index 150998b..ad81395 100644
--- a/src/drivers/i2c/max98373/chip.h
+++ b/src/drivers/i2c/max98373/chip.h
@@ -19,7 +19,7 @@
struct drivers_i2c_max98373_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */
uint32_t bus_speed;
- /* Set ‘1’ if I2S channel size is not 32bit. */
+ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode;
/* Identifier for chips */
uint32_t uid;
diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h
index 765bafd..6d3b9a5 100644
--- a/src/drivers/i2c/max98927/chip.h
+++ b/src/drivers/i2c/max98927/chip.h
@@ -19,7 +19,7 @@
struct drivers_i2c_max98927_config {
/* I2C Bus Frequency in Hertz (default 400kHz) */
unsigned int bus_speed;
- /* Set ‘1’ if I2S channel size is not 32bit. */
+ /* Set '1' if I2S channel size is not 32bit. */
bool interleave_mode;
/* Identifier for chips */
unsigned int uid;
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 3b0b507..27b6556 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -72,7 +72,7 @@
/*
* ODT settings :
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,
- * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
+ * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
* and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
index dba5901..7a3b0c0 100644
--- a/src/soc/intel/cannonlake/lockdown.c
+++ b/src/soc/intel/cannonlake/lockdown.c
@@ -60,8 +60,8 @@
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 79f6f70..1abe9cb 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -57,8 +57,8 @@
* GCS.BBS: (Boot BIOS Strap) This field determines the destination
* of accesses to the BIOS memory range.
* Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
+ * "0b": SPI
+ * "1b": LPC/eSPI
*/
pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
}
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 7bc923e..e40dc53 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -31,7 +31,7 @@
default n
help
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
- used to modulate the frequency of the Silicon Creations’ Fractional
+ used to modulate the frequency of the Silicon Creations' Fractional
PLL in order to reduce EMI.
endif
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 980adf5..5422deb 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -344,12 +344,12 @@
/*
* Configure the DPLL spread spectrum feature on memory clock.
* Configure sequence:
- * 1. PLL been configured as frac mode, and DACPD should be set to 1’b0.
+ * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0.
* 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with
* extern wave table).
- * 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0.
- * 4. Assert RESET = 1’b1 to SSMOD.
- * 5. RESET = 1’b0 on SSMOD.
+ * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0.
+ * 4. Assert RESET = 1'b1 to SSMOD.
+ * 5. RESET = 1'b0 on SSMOD.
* 6. Adjust SPREAD/DIVVAL/DOWNSPREAD.
*/
static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)
@@ -385,13 +385,13 @@
* value of SPREAD.
* SPREAD[4:0] Center Spread Down Spread
* 0 0 0
- * 1 ±0.1% -0.10%
- * 2 ±0.2% -0.20%
- * 3 ±0.3% -0.30%
- * 4 ±0.4% -0.40%
- * 5 ±0.5% -0.50%
+ * 1 +/-0.1% -0.10%
+ * 2 +/-0.2% -0.20%
+ * 3 +/-0.3% -0.30%
+ * 4 +/-0.4% -0.40%
+ * 5 +/-0.5% -0.50%
* ...
- * 31 ±3.1% -3.10%
+ * 31 +/-3.1% -3.10%
*/
write32(&cru_ptr->dpll_con[4],
RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT,
diff --git a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
index 2e9e763..3515078 100644
--- a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
+++ b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl
@@ -71,7 +71,7 @@
Package (4) { 0x0010ffff, 2, 0x00, 21 },
Package (4) { 0x0010ffff, 3, 0x00, 21 },
- /* AC’97 / MC’97 IRQ and INTG => IRQ22 */
+ /* AC'97 / MC'97 IRQ and INTG => IRQ22 */
Package (4) { 0x0011ffff, 0, 0x00, 22 },
Package (4) { 0x0011ffff, 1, 0x00, 22 },
Package (4) { 0x0011ffff, 2, 0x00, 22 },
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iedb78e24a286a51830c85724af0179995ed553be
Gerrit-Change-Number: 26434
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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