<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26434">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Remove non-ascii characters<br><br>Change-Id: Iedb78e24a286a51830c85724af0179995ed553be<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/drivers/i2c/max98373/chip.h<br>M src/drivers/i2c/max98927/chip.h<br>M src/soc/intel/apollolake/include/soc/meminit.h<br>M src/soc/intel/cannonlake/lockdown.c<br>M src/soc/intel/skylake/lockdown.c<br>M src/soc/rockchip/rk3399/Kconfig<br>M src/soc/rockchip/rk3399/clock.c<br>M src/southbridge/via/vt8237r/acpi/default_irq_route.asl<br>8 files changed, 19 insertions(+), 19 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/26434/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h</span><br><span>index 150998b..ad81395 100644</span><br><span>--- a/src/drivers/i2c/max98373/chip.h</span><br><span>+++ b/src/drivers/i2c/max98373/chip.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> struct drivers_i2c_max98373_config {</span><br><span> /* I2C Bus Frequency in Hertz (default 400kHz) */</span><br><span> uint32_t bus_speed;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set ‘1’ if I2S channel size is not 32bit. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set '1' if I2S channel size is not 32bit. */</span><br><span> bool interleave_mode;</span><br><span> /* Identifier for chips */</span><br><span> uint32_t uid;</span><br><span>diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h</span><br><span>index 765bafd..6d3b9a5 100644</span><br><span>--- a/src/drivers/i2c/max98927/chip.h</span><br><span>+++ b/src/drivers/i2c/max98927/chip.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> struct drivers_i2c_max98927_config {</span><br><span> /* I2C Bus Frequency in Hertz (default 400kHz) */</span><br><span> unsigned int bus_speed;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set ‘1’ if I2S channel size is not 32bit. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set '1' if I2S channel size is not 32bit. */</span><br><span> bool interleave_mode;</span><br><span> /* Identifier for chips */</span><br><span> unsigned int uid;</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>index 3b0b507..27b6556 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/meminit.h</span><br><span>@@ -72,7 +72,7 @@</span><br><span> /*</span><br><span> * ODT settings :</span><br><span> * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,</span><br><span style="color: hsl(0, 100%, 40%);">- * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,</span><br><span style="color: hsl(120, 100%, 40%);">+ * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,</span><br><span> * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.</span><br><span> *</span><br><span> * Note that the enum values correspond to the interpreted UPD fields</span><br><span>diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c</span><br><span>index dba5901..7a3b0c0 100644</span><br><span>--- a/src/soc/intel/cannonlake/lockdown.c</span><br><span>+++ b/src/soc/intel/cannonlake/lockdown.c</span><br><span>@@ -60,8 +60,8 @@</span><br><span> * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span> * of accesses to the BIOS memory range.</span><br><span> * Bits Description</span><br><span style="color: hsl(0, 100%, 40%);">- * “0b”: SPI</span><br><span style="color: hsl(0, 100%, 40%);">- * “1b”: LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * "0b": SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * "1b": LPC/eSPI</span><br><span> */</span><br><span> pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span> }</span><br><span>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c</span><br><span>index 79f6f70..1abe9cb 100644</span><br><span>--- a/src/soc/intel/skylake/lockdown.c</span><br><span>+++ b/src/soc/intel/skylake/lockdown.c</span><br><span>@@ -57,8 +57,8 @@</span><br><span> * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span> * of accesses to the BIOS memory range.</span><br><span> * Bits Description</span><br><span style="color: hsl(0, 100%, 40%);">- * “0b”: SPI</span><br><span style="color: hsl(0, 100%, 40%);">- * “1b”: LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * "0b": SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * "1b": LPC/eSPI</span><br><span> */</span><br><span> pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span> }</span><br><span>diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig</span><br><span>index 7bc923e..e40dc53 100644</span><br><span>--- a/src/soc/rockchip/rk3399/Kconfig</span><br><span>+++ b/src/soc/rockchip/rk3399/Kconfig</span><br><span>@@ -31,7 +31,7 @@</span><br><span> default n</span><br><span> help</span><br><span> Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit</span><br><span style="color: hsl(0, 100%, 40%);">- used to modulate the frequency of the Silicon Creations’ Fractional</span><br><span style="color: hsl(120, 100%, 40%);">+ used to modulate the frequency of the Silicon Creations' Fractional</span><br><span> PLL in order to reduce EMI.</span><br><span> </span><br><span> endif</span><br><span>diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c</span><br><span>index 980adf5..5422deb 100644</span><br><span>--- a/src/soc/rockchip/rk3399/clock.c</span><br><span>+++ b/src/soc/rockchip/rk3399/clock.c</span><br><span>@@ -344,12 +344,12 @@</span><br><span> /*</span><br><span> * Configure the DPLL spread spectrum feature on memory clock.</span><br><span> * Configure sequence:</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. PLL been configured as frac mode, and DACPD should be set to 1’b0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0.</span><br><span> * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with</span><br><span> * extern wave table).</span><br><span style="color: hsl(0, 100%, 40%);">- * 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0.</span><br><span style="color: hsl(0, 100%, 40%);">- * 4. Assert RESET = 1’b1 to SSMOD.</span><br><span style="color: hsl(0, 100%, 40%);">- * 5. RESET = 1’b0 on SSMOD.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 4. Assert RESET = 1'b1 to SSMOD.</span><br><span style="color: hsl(120, 100%, 40%);">+ * 5. RESET = 1'b0 on SSMOD.</span><br><span> * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD.</span><br><span> */</span><br><span> static void rkclk_set_dpllssc(struct pll_div *dpll_cfg)</span><br><span>@@ -385,13 +385,13 @@</span><br><span> * value of SPREAD.</span><br><span> * SPREAD[4:0] Center Spread Down Spread</span><br><span> * 0 0 0</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 ±0.1% -0.10%</span><br><span style="color: hsl(0, 100%, 40%);">- * 2 ±0.2% -0.20%</span><br><span style="color: hsl(0, 100%, 40%);">- * 3 ±0.3% -0.30%</span><br><span style="color: hsl(0, 100%, 40%);">- * 4 ±0.4% -0.40%</span><br><span style="color: hsl(0, 100%, 40%);">- * 5 ±0.5% -0.50%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 +/-0.1% -0.10%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2 +/-0.2% -0.20%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3 +/-0.3% -0.30%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 4 +/-0.4% -0.40%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 5 +/-0.5% -0.50%</span><br><span> * ...</span><br><span style="color: hsl(0, 100%, 40%);">- * 31 ±3.1% -3.10%</span><br><span style="color: hsl(120, 100%, 40%);">+ * 31 +/-3.1% -3.10%</span><br><span> */</span><br><span> write32(&cru_ptr->dpll_con[4],</span><br><span> RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT,</span><br><span>diff --git a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl</span><br><span>index 2e9e763..3515078 100644</span><br><span>--- a/src/southbridge/via/vt8237r/acpi/default_irq_route.asl</span><br><span>+++ b/src/southbridge/via/vt8237r/acpi/default_irq_route.asl</span><br><span>@@ -71,7 +71,7 @@</span><br><span> Package (4) { 0x0010ffff, 2, 0x00, 21 },</span><br><span> Package (4) { 0x0010ffff, 3, 0x00, 21 },</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* AC’97 / MC’97 IRQ and INTG => IRQ22 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* AC'97 / MC'97 IRQ and INTG => IRQ22 */</span><br><span> Package (4) { 0x0011ffff, 0, 0x00, 22 },</span><br><span> Package (4) { 0x0011ffff, 1, 0x00, 22 },</span><br><span> Package (4) { 0x0011ffff, 2, 0x00, 22 },</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26434">change 26434</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iedb78e24a286a51830c85724af0179995ed553be </div>
<div style="display:none"> Gerrit-Change-Number: 26434 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>