[coreboot-gerrit] Change in coreboot[master]: sb/amd/cimx/sb800: Get rid of device_t

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26414


Change subject: sb/amd/cimx/sb800: Get rid of device_t
......................................................................

sb/amd/cimx/sb800: Get rid of device_t

Use of device_t has been abandoned in ramstage.

Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/cimx/sb800/fan.c
M src/southbridge/amd/cimx/sb800/fan.h
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/lpc.c
M src/southbridge/amd/cimx/sb800/lpc.h
M src/southbridge/amd/cimx/sb800/spi.c
6 files changed, 16 insertions(+), 16 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/26414/1

diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index 5925330..e7749e4 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -14,14 +14,14 @@
  */
 
 #include <southbridge/amd/cimx/cimx_util.h>
-#include <device/device.h>	/* device_t */
+#include <device/device.h>	/* struct device **/
 #include <device/pci.h>		/* device_operations */
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
 #include "fan.h"
 
-void init_sb800_MANUAL_fans(device_t dev)
+void init_sb800_MANUAL_fans(struct device *dev)
 {
 	int i;
 	struct southbridge_amd_cimx_sb800_config *sb_chip =
@@ -54,7 +54,7 @@
 
 }
 
-void init_sb800_IMC_fans(device_t dev)
+void init_sb800_IMC_fans(struct device *dev)
 {
 
 	AMDSBCFG sb_config;
diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h
index 6542967..f31e486 100644
--- a/src/southbridge/amd/cimx/sb800/fan.h
+++ b/src/southbridge/amd/cimx/sb800/fan.h
@@ -17,8 +17,8 @@
 #define _SB800_FAN_H_
 
 #ifndef __PRE_RAM__
-void init_sb800_IMC_fans(device_t dev);
-void init_sb800_MANUAL_fans(device_t dev);
+void init_sb800_IMC_fans(struct device *dev);
+void init_sb800_MANUAL_fans(struct device *dev);
 #endif
 
 /* Fan Register Definitions */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 393eda0..4239d46 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -15,7 +15,7 @@
  */
 
 
-#include <device/device.h>	/* device_t */
+#include <device/device.h>	/* struct device **/
 #include <device/pci.h>		/* device_operations */
 #include <device/pci_ids.h>
 #include <bootstate.h>
@@ -118,7 +118,7 @@
 	.set_subsystem = pci_dev_set_subsystem,
 };
 
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
 
@@ -344,7 +344,7 @@
 /**
  * @brief SB Cimx entry point sbBeforePciInit wrapper
  */
-static void sb800_enable(device_t dev)
+static void sb800_enable(struct device *dev)
 {
 	struct southbridge_amd_cimx_sb800_config *sb_chip =
 		(struct southbridge_amd_cimx_sb800_config *)(dev->chip_info);
@@ -427,7 +427,7 @@
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 		{
-			device_t device;
+			struct device *device;
 			for (device = dev; device; device = device->sibling) {
 				if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15,0)) break;
 				sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index 4973558..40c0739 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <cbmem.h>
 
-void lpc_read_resources(device_t dev)
+void lpc_read_resources(struct device *dev)
 {
 	struct resource *res;
 
@@ -76,7 +76,7 @@
  * @param dev the device whose children's resources are to be enabled
  *
  */
-void lpc_enable_childrens_resources(device_t dev)
+void lpc_enable_childrens_resources(struct device *dev)
 {
 	struct bus *link;
 	u32 reg, reg_x;
@@ -88,7 +88,7 @@
 	reg_x = pci_read_config32(dev, 0x48);
 
 	for (link = dev->link_list; link; link = link->next) {
-		device_t child;
+		struct device *child;
 		for (child = link->children; child;
 		     child = child->sibling) {
 			if (child->enabled
diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h
index ee76b43..b478eb4 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.h
+++ b/src/southbridge/amd/cimx/sb800/lpc.h
@@ -21,8 +21,8 @@
 #define SPI_ROM_ENABLE                0x02
 #define SPI_BASE_ADDRESS              0xFEC10000
 
-void lpc_read_resources(device_t dev);
-void lpc_set_resources(device_t dev);
-void lpc_enable_childrens_resources(device_t dev);
+void lpc_read_resources(struct device *dev);
+void lpc_set_resources(struct device *dev);
+void lpc_enable_childrens_resources(struct device *dev);
 
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index 2c541e3..54dd77a 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -48,7 +48,7 @@
 
 void spi_init()
 {
-	device_t dev;
+	struct device *dev;
 
 	dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
 	spibar = pci_read_config32(dev, 0xA0) & ~0x1F;

-- 
To view, visit https://review.coreboot.org/26414
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62
Gerrit-Change-Number: 26414
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180519/ddb04ae3/attachment.html>