[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb600: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sat May 19 14:10:19 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26407
Change subject: sb/amd/sb600: Get rid of device_t
......................................................................
sb/amd/sb600: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/sb600/hda.c
M src/southbridge/amd/sb600/lpc.c
M src/southbridge/amd/sb600/sata.c
M src/southbridge/amd/sb600/sb600.c
M src/southbridge/amd/sb600/sb600.h
M src/southbridge/amd/sb600/sm.c
M src/southbridge/amd/sb600/usb.c
7 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26407/1
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index bb2b2b1..367866f 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -150,7 +150,7 @@
static u32 find_verb(u32 viddid, u32 ** verb)
{
- device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
+ struct device *azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
struct southbridge_amd_sb600_config *cfg =
(struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
if (!cfg)
@@ -265,7 +265,7 @@
void *base;
struct resource *res;
u32 codec_mask;
- device_t sm_dev;
+ struct device *sm_dev;
/* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
pm_iowrite(0x59, 0xB);
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 0541518..70699d0 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -31,11 +31,11 @@
#include <cpu/amd/powernow.h>
#include "sb600.h"
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
{
u8 byte;
u32 dword;
- device_t sm_dev;
+ struct device *sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -67,7 +67,7 @@
setup_i8254(); /* Initialize i8254 timers */
}
-static void sb600_lpc_read_resources(device_t dev)
+static void sb600_lpc_read_resources(struct device *dev)
{
struct resource *res;
@@ -103,7 +103,7 @@
* @param dev the device whose children's resources are to be enabled
*
*/
-static void sb600_lpc_enable_childrens_resources(device_t dev)
+static void sb600_lpc_enable_childrens_resources(struct device *dev)
{
struct bus *link;
u32 reg, reg_x;
@@ -115,7 +115,7 @@
reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device *child;
for (child = link->children; child;
child = child->sibling) {
if (child->enabled
@@ -214,7 +214,7 @@
pci_write_config8(dev, 0x74, wiosize);
}
-static void sb600_lpc_enable_resources(device_t dev)
+static void sb600_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
sb600_lpc_enable_childrens_resources(dev);
@@ -224,7 +224,7 @@
extern u16 pm_base;
-static void southbridge_acpi_fill_ssdt_generator(device_t device) {
+static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
amd_generate_powernow(pm_base + 8, 6, 1);
}
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index dbb4ec5..650bb39 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -66,7 +66,7 @@
struct southbridge_ati_sb600_config *conf;
conf = dev->chip_info;
- device_t sm_dev;
+ struct device *sm_dev;
/* SATA SMBus Disable */
/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c
index 9e57ac2..124199b 100644
--- a/src/southbridge/amd/sb600/sb600.c
+++ b/src/southbridge/amd/sb600/sb600.c
@@ -23,9 +23,9 @@
#include <device/pci_ops.h>
#include "sb600.h"
-static device_t find_sm_dev(device_t dev, u32 devfn)
+static struct device *find_sm_dev(struct device *dev, u32 devfn)
{
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!sm_dev)
@@ -45,7 +45,7 @@
return sm_dev;
}
-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -88,7 +88,7 @@
return pmio_read_index(PM2_INDEX, reg);
}
-static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
+static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos,
u32 mask, u32 val)
{
u8 reg_old, reg;
@@ -100,10 +100,10 @@
}
}
-void sb600_enable(device_t dev)
+void sb600_enable(struct device *dev)
{
- device_t sm_dev = 0;
- device_t bus_dev = 0;
+ struct device *sm_dev = 0;
+ struct device *bus_dev = 0;
int index = -1;
u32 deviceid;
u32 vendorid;
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 94ee861..ba994b8 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -36,8 +36,8 @@
extern u8 pm2_ioread(u8 reg);
#ifndef __SIMPLE_DEVICE__
-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
-void sb600_enable(device_t dev);
+extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
+void sb600_enable(struct device *dev);
#endif
void sb600_lpc_port80(void);
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 5773ae2..371ffcd 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -40,7 +40,7 @@
* SB600 enables all USB controllers by default in SMBUS Control.
* SB600 enables SATA by default in SMBUS Control.
*/
-static void sm_init(device_t dev)
+static void sm_init(struct device *dev)
{
u8 byte;
u8 byte_old;
@@ -216,7 +216,7 @@
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
{
u32 device;
struct resource *res;
@@ -230,7 +230,7 @@
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
{
u32 device;
struct resource *res;
@@ -244,7 +244,7 @@
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u32 device;
struct resource *res;
@@ -258,7 +258,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u32 device;
struct resource *res;
@@ -278,7 +278,7 @@
.write_byte = lsmbus_write_byte,
};
-static void sb600_sm_read_resources(device_t dev)
+static void sb600_sm_read_resources(struct device *dev)
{
struct resource *res;
u8 byte;
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 3be2312..85df6c5 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -33,7 +33,7 @@
u32 dword;
/* Enable OHCI0-4 and EHCI Controllers */
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0x68);
byte |= 0x3F;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689
Gerrit-Change-Number: 26407
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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