<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26407">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/sb600: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sb600/hda.c<br>M src/southbridge/amd/sb600/lpc.c<br>M src/southbridge/amd/sb600/sata.c<br>M src/southbridge/amd/sb600/sb600.c<br>M src/southbridge/amd/sb600/sb600.h<br>M src/southbridge/amd/sb600/sm.c<br>M src/southbridge/amd/sb600/usb.c<br>7 files changed, 26 insertions(+), 26 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/26407/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c</span><br><span>index bb2b2b1..367866f 100644</span><br><span>--- a/src/southbridge/amd/sb600/hda.c</span><br><span>+++ b/src/southbridge/amd/sb600/hda.c</span><br><span>@@ -150,7 +150,7 @@</span><br><span> </span><br><span> static u32 find_verb(u32 viddid, u32 ** verb)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));</span><br><span>    struct southbridge_amd_sb600_config *cfg =</span><br><span>       (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;</span><br><span>         if (!cfg)</span><br><span>@@ -265,7 +265,7 @@</span><br><span>      void *base;</span><br><span>  struct resource *res;</span><br><span>        u32 codec_mask;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   /* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */</span><br><span>         pm_iowrite(0x59, 0xB);</span><br><span>diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c</span><br><span>index 0541518..70699d0 100644</span><br><span>--- a/src/southbridge/amd/sb600/lpc.c</span><br><span>+++ b/src/southbridge/amd/sb600/lpc.c</span><br><span>@@ -31,11 +31,11 @@</span><br><span> #include <cpu/amd/powernow.h></span><br><span> #include "sb600.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_init(struct device *dev)</span><br><span> {</span><br><span>    u8 byte;</span><br><span>     u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   /* Enable the LPC Controller */</span><br><span>      sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>@@ -67,7 +67,7 @@</span><br><span>   setup_i8254(); /* Initialize i8254 timers */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb600_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb600_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>       struct resource *res;</span><br><span> </span><br><span>@@ -103,7 +103,7 @@</span><br><span>  * @param dev the device whose children's resources are to be enabled</span><br><span>  *</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sb600_lpc_enable_childrens_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb600_lpc_enable_childrens_resources(struct device *dev)</span><br><span> {</span><br><span>   struct bus *link;</span><br><span>    u32 reg, reg_x;</span><br><span>@@ -115,7 +115,7 @@</span><br><span>        reg_x = pci_read_config32(dev, 0x48);</span><br><span> </span><br><span>    for (link = dev->link_list; link; link = link->next) {</span><br><span style="color: hsl(0, 100%, 40%);">-            device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+               struct device *child;</span><br><span>                for (child = link->children; child;</span><br><span>                    child = child->sibling) {</span><br><span>                    if (child->enabled</span><br><span>@@ -214,7 +214,7 @@</span><br><span>  pci_write_config8(dev, 0x74, wiosize);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb600_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb600_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>         pci_dev_enable_resources(dev);</span><br><span>       sb600_lpc_enable_childrens_resources(dev);</span><br><span>@@ -224,7 +224,7 @@</span><br><span> </span><br><span> extern u16 pm_base;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_acpi_fill_ssdt_generator(device_t device) {</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_acpi_fill_ssdt_generator(struct device *device) {</span><br><span>        amd_generate_powernow(pm_base + 8, 6, 1);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c</span><br><span>index dbb4ec5..650bb39 100644</span><br><span>--- a/src/southbridge/amd/sb600/sata.c</span><br><span>+++ b/src/southbridge/amd/sb600/sata.c</span><br><span>@@ -66,7 +66,7 @@</span><br><span>  struct southbridge_ati_sb600_config *conf;</span><br><span>   conf = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       /* SATA SMBus Disable */</span><br><span>     /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */</span><br><span>         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c</span><br><span>index 9e57ac2..124199b 100644</span><br><span>--- a/src/southbridge/amd/sb600/sb600.c</span><br><span>+++ b/src/southbridge/amd/sb600/sb600.c</span><br><span>@@ -23,9 +23,9 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include "sb600.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static device_t find_sm_dev(device_t dev, u32 devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *find_sm_dev(struct device *dev, u32 devfn)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   sm_dev = dev_find_slot(dev->bus->secondary, devfn);</span><br><span>    if (!sm_dev)</span><br><span>@@ -45,7 +45,7 @@</span><br><span>     return sm_dev;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>         u32 reg_old, reg;</span><br><span>    reg = reg_old = pci_read_config32(sm_dev, reg_pos);</span><br><span>@@ -88,7 +88,7 @@</span><br><span>      return pmio_read_index(PM2_INDEX, reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos,</span><br><span>                                  u32 mask, u32 val)</span><br><span> {</span><br><span>     u8 reg_old, reg;</span><br><span>@@ -100,10 +100,10 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb600_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sb600_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t sm_dev = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t bus_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *sm_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *bus_dev = 0;</span><br><span>  int index = -1;</span><br><span>      u32 deviceid;</span><br><span>        u32 vendorid;</span><br><span>diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h</span><br><span>index 94ee861..ba994b8 100644</span><br><span>--- a/src/southbridge/amd/sb600/sb600.h</span><br><span>+++ b/src/southbridge/amd/sb600/sb600.h</span><br><span>@@ -36,8 +36,8 @@</span><br><span> extern u8 pm2_ioread(u8 reg);</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(0, 100%, 40%);">-void sb600_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb600_enable(struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> void sb600_lpc_port80(void);</span><br><span>diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c</span><br><span>index 5773ae2..371ffcd 100644</span><br><span>--- a/src/southbridge/amd/sb600/sm.c</span><br><span>+++ b/src/southbridge/amd/sb600/sm.c</span><br><span>@@ -40,7 +40,7 @@</span><br><span> * SB600 enables all USB controllers by default in SMBUS Control.</span><br><span> * SB600 enables SATA by default in SMBUS Control.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sm_init(struct device *dev)</span><br><span> {</span><br><span>    u8 byte;</span><br><span>     u8 byte_old;</span><br><span>@@ -216,7 +216,7 @@</span><br><span>   abcfg_reg(0x50, 1 << 3, 1 << 3);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span>         u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -230,7 +230,7 @@</span><br><span>  return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, u8 val)</span><br><span> {</span><br><span>     u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -244,7 +244,7 @@</span><br><span>  return do_smbus_send_byte(res->base, device, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>        u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -258,7 +258,7 @@</span><br><span>  return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -278,7 +278,7 @@</span><br><span>  .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb600_sm_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb600_sm_read_resources(struct device *dev)</span><br><span> {</span><br><span>    struct resource *res;</span><br><span>        u8 byte;</span><br><span>diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c</span><br><span>index 3be2312..85df6c5 100644</span><br><span>--- a/src/southbridge/amd/sb600/usb.c</span><br><span>+++ b/src/southbridge/amd/sb600/usb.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span>        u32 dword;</span><br><span> </span><br><span>       /* Enable OHCI0-4 and EHCI Controllers */</span><br><span style="color: hsl(0, 100%, 40%);">-       device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>       byte = pci_read_config8(sm_dev, 0x68);</span><br><span>       byte |= 0x3F;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26407">change 26407</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26407"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689 </div>
<div style="display:none"> Gerrit-Change-Number: 26407 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>