[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sat May 19 12:38:32 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26406
Change subject: sb/amd/sb700: Get rid of device_t
......................................................................
sb/amd/sb700: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I53acc7dd4ddf2787fc1e59d604cadc4f3b4cb49c
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/sb700/hda.c
M src/southbridge/amd/sb700/lpc.c
M src/southbridge/amd/sb700/sata.c
M src/southbridge/amd/sb700/sb700.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb700/sm.c
M src/southbridge/amd/sb700/spi.c
M src/southbridge/amd/sb700/usb.c
8 files changed, 28 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/26406/1
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index f89f3bb..af2c837 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -165,7 +165,7 @@
void *base;
struct resource *res;
u32 codec_mask;
- device_t sm_dev;
+ struct device *sm_dev;
/* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */
byte = pm_ioread(0x59);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index a56ccf0..6569e39 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -32,11 +32,11 @@
#include <cpu/amd/powernow.h>
#include "sb700.h"
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
{
u8 byte;
u32 dword;
- device_t sm_dev;
+ struct device *sm_dev;
printk(BIOS_SPEW, "%s\n", __func__);
@@ -82,7 +82,7 @@
setup_i8254(); /* Initialize i8254 timers */
}
-static void sb700_lpc_read_resources(device_t dev)
+static void sb700_lpc_read_resources(struct device *dev)
{
struct resource *res;
@@ -129,7 +129,7 @@
* @param dev the device whose children's resources are to be enabled
*
*/
-static void sb700_lpc_enable_childrens_resources(device_t dev)
+static void sb700_lpc_enable_childrens_resources(struct device *dev)
{
struct bus *link;
u32 reg, reg_x;
@@ -141,7 +141,7 @@
reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device *child;
for (child = link->children; child;
child = child->sibling) {
if (!(child->enabled
@@ -242,7 +242,7 @@
pci_write_config8(dev, 0x74, wiosize);
}
-static void sb700_lpc_enable_resources(device_t dev)
+static void sb700_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
sb700_lpc_enable_childrens_resources(dev);
@@ -250,7 +250,7 @@
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void southbridge_acpi_fill_ssdt_generator(device_t device) {
+static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1);
}
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 2045d52..6caffee 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -133,7 +133,7 @@
if (get_option(&nvram, "sata_alpm") == CB_SUCCESS)
sata_alpm_enable = !!nvram;
- device_t sm_dev;
+ struct device *sm_dev;
/* SATA SMBus Disable */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -170,7 +170,7 @@
byte |= (1 << 3);
pci_write_config8(sm_dev, 0xad, byte);
- device_t ide_dev;
+ struct device *ide_dev;
/* IDE Device */
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 1068721..c68bf55 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -23,9 +23,9 @@
#include <device/pci_ops.h>
#include "sb700.h"
-static device_t find_sm_dev(device_t dev, u32 devfn)
+static struct device *find_sm_dev(struct device *dev, u32 devfn)
{
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!sm_dev)
@@ -45,7 +45,7 @@
return sm_dev;
}
-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -88,7 +88,7 @@
return pmio_read_index(PM2_INDEX, reg);
}
-static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
+static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos,
u32 mask, u32 val)
{
u8 reg_old, reg;
@@ -100,10 +100,10 @@
}
}
-void sb7xx_51xx_enable(device_t dev)
+void sb7xx_51xx_enable(struct device *dev)
{
- device_t sm_dev = 0;
- device_t bus_dev = 0;
+ struct device *sm_dev = 0;
+ struct device *bus_dev = 0;
int index = -1;
u32 deviceid;
u32 vendorid;
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 6b34502..f2a4666 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -43,7 +43,7 @@
extern void pm2_iowrite(u8 reg, u8 value);
extern u8 pm2_ioread(u8 reg);
#ifndef __SIMPLE_DEVICE__
-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
#endif
#define REV_SB700_A11 0x11
@@ -59,7 +59,7 @@
#define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28)
#ifndef __SIMPLE_DEVICE__
-void sb7xx_51xx_enable(device_t dev);
+void sb7xx_51xx_enable(struct device *dev);
#endif
#ifdef __PRE_RAM__
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 77ec722..436854e 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -58,7 +58,7 @@
* SB700 enables all USB controllers by default in SMBUS Control.
* SB700 enables SATA by default in SMBUS Control.
*/
-static void sm_init(device_t dev)
+static void sm_init(struct device *dev)
{
u8 byte;
u8 byte_old;
@@ -352,7 +352,7 @@
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
{
u32 device;
struct resource *res;
@@ -369,7 +369,7 @@
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
{
u32 device;
struct resource *res;
@@ -386,7 +386,7 @@
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u32 device;
struct resource *res;
@@ -403,7 +403,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u32 device;
struct resource *res;
@@ -427,7 +427,7 @@
.write_byte = lsmbus_write_byte,
};
-static void sb700_sm_read_resources(device_t dev)
+static void sb700_sm_read_resources(struct device *dev)
{
struct resource *res;
diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c
index d3aa296..1fa29aa 100644
--- a/src/southbridge/amd/sb700/spi.c
+++ b/src/southbridge/amd/sb700/spi.c
@@ -29,7 +29,7 @@
static uint32_t get_spi_bar(void)
{
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
return pci_read_config32(dev, 0xa0) & ~0x1f;
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 6276008..12b9dd6 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -34,7 +34,7 @@
u32 dword;
/* 6.1 Enable OHCI0-4 and EHCI Controllers */
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0x68);
byte |= 0xFF;
@@ -79,7 +79,7 @@
{
uint32_t dword;
void *usb2_bar0;
- device_t sm_dev;
+ struct device *sm_dev;
uint8_t rev;
uint8_t ehci_async_data_cache;
uint8_t nvram;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I53acc7dd4ddf2787fc1e59d604cadc4f3b4cb49c
Gerrit-Change-Number: 26406
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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