<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26406">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/sb700: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I53acc7dd4ddf2787fc1e59d604cadc4f3b4cb49c<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sb700/hda.c<br>M src/southbridge/amd/sb700/lpc.c<br>M src/southbridge/amd/sb700/sata.c<br>M src/southbridge/amd/sb700/sb700.c<br>M src/southbridge/amd/sb700/sb700.h<br>M src/southbridge/amd/sb700/sm.c<br>M src/southbridge/amd/sb700/spi.c<br>M src/southbridge/amd/sb700/usb.c<br>8 files changed, 28 insertions(+), 28 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/26406/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c</span><br><span>index f89f3bb..af2c837 100644</span><br><span>--- a/src/southbridge/amd/sb700/hda.c</span><br><span>+++ b/src/southbridge/amd/sb700/hda.c</span><br><span>@@ -165,7 +165,7 @@</span><br><span>   void *base;</span><br><span>  struct resource *res;</span><br><span>        u32 codec_mask;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   /* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */</span><br><span>       byte = pm_ioread(0x59);</span><br><span>diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c</span><br><span>index a56ccf0..6569e39 100644</span><br><span>--- a/src/southbridge/amd/sb700/lpc.c</span><br><span>+++ b/src/southbridge/amd/sb700/lpc.c</span><br><span>@@ -32,11 +32,11 @@</span><br><span> #include <cpu/amd/powernow.h></span><br><span> #include "sb700.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_init(struct device *dev)</span><br><span> {</span><br><span>   u8 byte;</span><br><span>     u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   printk(BIOS_SPEW, "%s\n", __func__);</span><br><span> </span><br><span>@@ -82,7 +82,7 @@</span><br><span>       setup_i8254(); /* Initialize i8254 timers */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb700_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb700_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>       struct resource *res;</span><br><span> </span><br><span>@@ -129,7 +129,7 @@</span><br><span>  * @param dev the device whose children's resources are to be enabled</span><br><span>  *</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sb700_lpc_enable_childrens_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb700_lpc_enable_childrens_resources(struct device *dev)</span><br><span> {</span><br><span>   struct bus *link;</span><br><span>    u32 reg, reg_x;</span><br><span>@@ -141,7 +141,7 @@</span><br><span>        reg_x = pci_read_config32(dev, 0x48);</span><br><span> </span><br><span>    for (link = dev->link_list; link; link = link->next) {</span><br><span style="color: hsl(0, 100%, 40%);">-            device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+               struct device *child;</span><br><span>                for (child = link->children; child;</span><br><span>                    child = child->sibling) {</span><br><span>                    if (!(child->enabled</span><br><span>@@ -242,7 +242,7 @@</span><br><span>        pci_write_config8(dev, 0x74, wiosize);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb700_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb700_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>         pci_dev_enable_resources(dev);</span><br><span>       sb700_lpc_enable_childrens_resources(dev);</span><br><span>@@ -250,7 +250,7 @@</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_acpi_fill_ssdt_generator(device_t device) {</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_acpi_fill_ssdt_generator(struct device *device) {</span><br><span>    amd_generate_powernow(ACPI_CPU_CONTROL, 6, 1);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c</span><br><span>index 2045d52..6caffee 100644</span><br><span>--- a/src/southbridge/amd/sb700/sata.c</span><br><span>+++ b/src/southbridge/amd/sb700/sata.c</span><br><span>@@ -133,7 +133,7 @@</span><br><span>   if (get_option(&nvram, "sata_alpm") == CB_SUCCESS)</span><br><span>             sata_alpm_enable = !!nvram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       /* SATA SMBus Disable */</span><br><span>     sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span> </span><br><span>@@ -170,7 +170,7 @@</span><br><span>     byte |= (1 << 3);</span><br><span>      pci_write_config8(sm_dev, 0xad, byte);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-      device_t ide_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *ide_dev;</span><br><span>      /* IDE Device */</span><br><span>     ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c</span><br><span>index 1068721..c68bf55 100644</span><br><span>--- a/src/southbridge/amd/sb700/sb700.c</span><br><span>+++ b/src/southbridge/amd/sb700/sb700.c</span><br><span>@@ -23,9 +23,9 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include "sb700.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static device_t find_sm_dev(device_t dev, u32 devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *find_sm_dev(struct device *dev, u32 devfn)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   sm_dev = dev_find_slot(dev->bus->secondary, devfn);</span><br><span>    if (!sm_dev)</span><br><span>@@ -45,7 +45,7 @@</span><br><span>     return sm_dev;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>         u32 reg_old, reg;</span><br><span>    reg = reg_old = pci_read_config32(sm_dev, reg_pos);</span><br><span>@@ -88,7 +88,7 @@</span><br><span>      return pmio_read_index(PM2_INDEX, reg);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos,</span><br><span>                                  u32 mask, u32 val)</span><br><span> {</span><br><span>     u8 reg_old, reg;</span><br><span>@@ -100,10 +100,10 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb7xx_51xx_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sb7xx_51xx_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t sm_dev = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t bus_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *sm_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *bus_dev = 0;</span><br><span>  int index = -1;</span><br><span>      u32 deviceid;</span><br><span>        u32 vendorid;</span><br><span>diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h</span><br><span>index 6b34502..f2a4666 100644</span><br><span>--- a/src/southbridge/amd/sb700/sb700.h</span><br><span>+++ b/src/southbridge/amd/sb700/sb700.h</span><br><span>@@ -43,7 +43,7 @@</span><br><span> extern void pm2_iowrite(u8 reg, u8 value);</span><br><span> extern u8 pm2_ioread(u8 reg);</span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span> #endif</span><br><span> </span><br><span> #define REV_SB700_A11   0x11</span><br><span>@@ -59,7 +59,7 @@</span><br><span> #define get_sb700_revision(sm_dev)  (pci_read_config8((sm_dev), 0x08) - 0x28)</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-void sb7xx_51xx_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb7xx_51xx_enable(struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> #ifdef __PRE_RAM__</span><br><span>diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c</span><br><span>index 77ec722..436854e 100644</span><br><span>--- a/src/southbridge/amd/sb700/sm.c</span><br><span>+++ b/src/southbridge/amd/sb700/sm.c</span><br><span>@@ -58,7 +58,7 @@</span><br><span> * SB700 enables all USB controllers by default in SMBUS Control.</span><br><span> * SB700 enables SATA by default in SMBUS Control.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sm_init(struct device *dev)</span><br><span> {</span><br><span>      u8 byte;</span><br><span>     u8 byte_old;</span><br><span>@@ -352,7 +352,7 @@</span><br><span>   abcfg_reg(0x50, 1 << 3, 1 << 3);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span>         u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -369,7 +369,7 @@</span><br><span>  return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, u8 val)</span><br><span> {</span><br><span>     u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -386,7 +386,7 @@</span><br><span>  return do_smbus_send_byte(res->base, device, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>        u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -403,7 +403,7 @@</span><br><span>  return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -427,7 +427,7 @@</span><br><span>  .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb700_sm_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb700_sm_read_resources(struct device *dev)</span><br><span> {</span><br><span>    struct resource *res;</span><br><span> </span><br><span>diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c</span><br><span>index d3aa296..1fa29aa 100644</span><br><span>--- a/src/southbridge/amd/sb700/spi.c</span><br><span>+++ b/src/southbridge/amd/sb700/spi.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> static uint32_t get_spi_bar(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> </span><br><span>      dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));</span><br><span>  return pci_read_config32(dev, 0xa0) & ~0x1f;</span><br><span>diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c</span><br><span>index 6276008..12b9dd6 100644</span><br><span>--- a/src/southbridge/amd/sb700/usb.c</span><br><span>+++ b/src/southbridge/amd/sb700/usb.c</span><br><span>@@ -34,7 +34,7 @@</span><br><span>        u32 dword;</span><br><span> </span><br><span>       /* 6.1 Enable OHCI0-4 and EHCI Controllers */</span><br><span style="color: hsl(0, 100%, 40%);">-   device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>       byte = pci_read_config8(sm_dev, 0x68);</span><br><span>       byte |= 0xFF;</span><br><span>@@ -79,7 +79,7 @@</span><br><span> {</span><br><span>       uint32_t dword;</span><br><span>      void *usb2_bar0;</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       uint8_t rev;</span><br><span>         uint8_t ehci_async_data_cache;</span><br><span>       uint8_t nvram;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26406">change 26406</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div ite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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I53acc7dd4ddf2787fc1e59d604cadc4f3b4cb49c </div>
<div style="display:none"> Gerrit-Change-Number: 26406 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>