[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb800: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sat May 19 12:33:48 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26405
Change subject: sb/amd/sb800: Get rid of device_t
......................................................................
sb/amd/sb800: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Ie48b42cf2999df075e23dc8ba185934b4e600157
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/sb800/lpc.c
M src/southbridge/amd/sb800/sata.c
M src/southbridge/amd/sb800/sb800.c
M src/southbridge/amd/sb800/sb800.h
M src/southbridge/amd/sb800/sm.c
M src/southbridge/amd/sb800/usb.c
6 files changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/26405/1
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index f15fed3..3bbf823 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -28,11 +28,11 @@
#include <arch/acpi.h>
#include "sb800.h"
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
{
u8 byte;
u32 dword;
- device_t sm_dev;
+ struct device *sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -73,7 +73,7 @@
setup_i8254(); /* Initialize i8254 timers */
}
-static void sb800_lpc_read_resources(device_t dev)
+static void sb800_lpc_read_resources(struct device *dev)
{
struct resource *res;
@@ -121,7 +121,7 @@
* @param dev the device whose children's resources are to be enabled
*
*/
-static void sb800_lpc_enable_childrens_resources(device_t dev)
+static void sb800_lpc_enable_childrens_resources(struct device *dev)
{
struct bus *link;
u32 reg, reg_x;
@@ -133,7 +133,7 @@
reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device *child;
for (child = link->children; child;
child = child->sibling) {
if (child->enabled
@@ -232,7 +232,7 @@
pci_write_config8(dev, 0x74, wiosize);
}
-static void sb800_lpc_enable_resources(device_t dev)
+static void sb800_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
sb800_lpc_enable_childrens_resources(dev);
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 978ccec..15b2527 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -85,7 +85,7 @@
struct southbridge_ati_sb800_config *conf;
conf = dev->chip_info;
- device_t sm_dev;
+ struct device *sm_dev;
/* SATA SMBus Disable */
/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
index 8062ede..c23fae9 100644
--- a/src/southbridge/amd/sb800/sb800.c
+++ b/src/southbridge/amd/sb800/sb800.c
@@ -24,9 +24,9 @@
#include "sb800.h"
#include "smbus.h"
-static device_t find_sm_dev(device_t dev, u32 devfn)
+static struct device *find_sm_dev(struct device *dev, u32 devfn)
{
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!sm_dev)
@@ -46,7 +46,7 @@
return sm_dev;
}
-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)
{
u32 reg_old, reg;
reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -140,7 +140,7 @@
/* PCIe General Purpose Ports */
/* v:1814, d:3090. cp421A */
-static void set_sb800_gpp(device_t dev)
+static void set_sb800_gpp(struct device *dev)
{
struct southbridge_amd_sb800_config *conf;
u32 imp_rb, lc_status;
@@ -224,10 +224,10 @@
printk(BIOS_DEBUG, "lc_status=%x\n", lc_status);
}
-void sb800_enable(device_t dev)
+void sb800_enable(struct device *dev)
{
- device_t sm_dev = 0;
- device_t bus_dev = 0;
+ struct device *sm_dev = 0;
+ struct device *bus_dev = 0;
int index = -1;
u32 deviceid;
u32 vendorid;
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index b36d9bf..a65c68a9 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -44,7 +44,7 @@
u8 pm2_ioread(u8 reg);
#ifndef __SIMPLE_DEVICE__
-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
#endif
#define REV_SB800_A11 0x11
@@ -60,7 +60,7 @@
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
#else
-void sb800_enable(device_t dev);
+void sb800_enable(struct device *dev);
#endif
#endif /* SB800_H */
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index ba9e806..d4ed3cc 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -76,7 +76,7 @@
* SB800 enables SATA by default in SMBUS Control.
*/
-static void sm_init(device_t dev)
+static void sm_init(struct device *dev)
{
u8 byte;
@@ -189,7 +189,7 @@
abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700);
}
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
{
u32 device;
struct resource *res;
@@ -203,7 +203,7 @@
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
{
u32 device;
struct resource *res;
@@ -217,7 +217,7 @@
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u32 device;
struct resource *res;
@@ -231,7 +231,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u32 device;
struct resource *res;
@@ -251,7 +251,7 @@
.write_byte = lsmbus_write_byte,
};
-static void sb800_sm_read_resources(device_t dev)
+static void sb800_sm_read_resources(struct device *dev)
{
struct resource *res;
u8 byte;
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 464747d..2318a8f 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -55,7 +55,7 @@
{
u32 dword;
void *usb2_bar0;
- device_t sm_dev;
+ struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
//rev = get_sb800_revision(sm_dev);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie48b42cf2999df075e23dc8ba185934b4e600157
Gerrit-Change-Number: 26405
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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