<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26405">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/sb800: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: Ie48b42cf2999df075e23dc8ba185934b4e600157<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sb800/lpc.c<br>M src/southbridge/amd/sb800/sata.c<br>M src/southbridge/amd/sb800/sb800.c<br>M src/southbridge/amd/sb800/sb800.h<br>M src/southbridge/amd/sb800/sm.c<br>M src/southbridge/amd/sb800/usb.c<br>6 files changed, 23 insertions(+), 23 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/26405/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c</span><br><span>index f15fed3..3bbf823 100644</span><br><span>--- a/src/southbridge/amd/sb800/lpc.c</span><br><span>+++ b/src/southbridge/amd/sb800/lpc.c</span><br><span>@@ -28,11 +28,11 @@</span><br><span> #include <arch/acpi.h></span><br><span> #include "sb800.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void lpc_init(struct device *dev)</span><br><span> {</span><br><span>    u8 byte;</span><br><span>     u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   /* Enable the LPC Controller */</span><br><span>      sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>@@ -73,7 +73,7 @@</span><br><span>   setup_i8254(); /* Initialize i8254 timers */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb800_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb800_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>       struct resource *res;</span><br><span> </span><br><span>@@ -121,7 +121,7 @@</span><br><span>  * @param dev the device whose children's resources are to be enabled</span><br><span>  *</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void sb800_lpc_enable_childrens_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb800_lpc_enable_childrens_resources(struct device *dev)</span><br><span> {</span><br><span>   struct bus *link;</span><br><span>    u32 reg, reg_x;</span><br><span>@@ -133,7 +133,7 @@</span><br><span>        reg_x = pci_read_config32(dev, 0x48);</span><br><span> </span><br><span>    for (link = dev->link_list; link; link = link->next) {</span><br><span style="color: hsl(0, 100%, 40%);">-            device_t child;</span><br><span style="color: hsl(120, 100%, 40%);">+               struct device *child;</span><br><span>                for (child = link->children; child;</span><br><span>                    child = child->sibling) {</span><br><span>                    if (child->enabled</span><br><span>@@ -232,7 +232,7 @@</span><br><span>  pci_write_config8(dev, 0x74, wiosize);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb800_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb800_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span>         pci_dev_enable_resources(dev);</span><br><span>       sb800_lpc_enable_childrens_resources(dev);</span><br><span>diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c</span><br><span>index 978ccec..15b2527 100644</span><br><span>--- a/src/southbridge/amd/sb800/sata.c</span><br><span>+++ b/src/southbridge/amd/sb800/sata.c</span><br><span>@@ -85,7 +85,7 @@</span><br><span>  struct southbridge_ati_sb800_config *conf;</span><br><span>   conf = dev->chip_info;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-   device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span>       /* SATA SMBus Disable */</span><br><span>     /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */</span><br><span>         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c</span><br><span>index 8062ede..c23fae9 100644</span><br><span>--- a/src/southbridge/amd/sb800/sb800.c</span><br><span>+++ b/src/southbridge/amd/sb800/sb800.c</span><br><span>@@ -24,9 +24,9 @@</span><br><span> #include "sb800.h"</span><br><span> #include "smbus.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static device_t find_sm_dev(device_t dev, u32 devfn)</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *find_sm_dev(struct device *dev, u32 devfn)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   sm_dev = dev_find_slot(dev->bus->secondary, devfn);</span><br><span>    if (!sm_dev)</span><br><span>@@ -46,7 +46,7 @@</span><br><span>     return sm_dev;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span style="color: hsl(120, 100%, 40%);">+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)</span><br><span> {</span><br><span>         u32 reg_old, reg;</span><br><span>    reg = reg_old = pci_read_config32(sm_dev, reg_pos);</span><br><span>@@ -140,7 +140,7 @@</span><br><span> </span><br><span> /* PCIe General Purpose Ports */</span><br><span> /* v:1814, d:3090. cp421A */</span><br><span style="color: hsl(0, 100%, 40%);">-static void set_sb800_gpp(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_sb800_gpp(struct device *dev)</span><br><span> {</span><br><span>         struct southbridge_amd_sb800_config *conf;</span><br><span>   u32 imp_rb, lc_status;</span><br><span>@@ -224,10 +224,10 @@</span><br><span>       printk(BIOS_DEBUG, "lc_status=%x\n", lc_status);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void sb800_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void sb800_enable(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t sm_dev = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t bus_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *sm_dev = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *bus_dev = 0;</span><br><span>  int index = -1;</span><br><span>      u32 deviceid;</span><br><span>        u32 vendorid;</span><br><span>diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h</span><br><span>index b36d9bf..a65c68a9 100644</span><br><span>--- a/src/southbridge/amd/sb800/sb800.h</span><br><span>+++ b/src/southbridge/amd/sb800/sb800.h</span><br><span>@@ -44,7 +44,7 @@</span><br><span> u8 pm2_ioread(u8 reg);</span><br><span> </span><br><span> #ifndef __SIMPLE_DEVICE__</span><br><span style="color: hsl(0, 100%, 40%);">-void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span style="color: hsl(120, 100%, 40%);">+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);</span><br><span> #endif</span><br><span> </span><br><span> #define REV_SB800_A11 0x11</span><br><span>@@ -60,7 +60,7 @@</span><br><span> int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);</span><br><span> </span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-void sb800_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void sb800_enable(struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> #endif /* SB800_H */</span><br><span>diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c</span><br><span>index ba9e806..d4ed3cc 100644</span><br><span>--- a/src/southbridge/amd/sb800/sm.c</span><br><span>+++ b/src/southbridge/amd/sb800/sm.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> * SB800 enables SATA by default in SMBUS Control.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sm_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sm_init(struct device *dev)</span><br><span> {</span><br><span>      u8 byte;</span><br><span> </span><br><span>@@ -189,7 +189,7 @@</span><br><span>   abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_recv_byte(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_recv_byte(struct device *dev)</span><br><span> {</span><br><span>     u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -203,7 +203,7 @@</span><br><span>  return do_smbus_recv_byte(res->base, device);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_send_byte(device_t dev, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_send_byte(struct device *dev, u8 val)</span><br><span> {</span><br><span>     u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -217,7 +217,7 @@</span><br><span>  return do_smbus_send_byte(res->base, device, val);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>        u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -231,7 +231,7 @@</span><br><span>  return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span>  u32 device;</span><br><span>  struct resource *res;</span><br><span>@@ -251,7 +251,7 @@</span><br><span>  .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sb800_sm_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sb800_sm_read_resources(struct device *dev)</span><br><span> {</span><br><span>    struct resource *res;</span><br><span>        u8 byte;</span><br><span>diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c</span><br><span>index 464747d..2318a8f 100644</span><br><span>--- a/src/southbridge/amd/sb800/usb.c</span><br><span>+++ b/src/southbridge/amd/sb800/usb.c</span><br><span>@@ -55,7 +55,7 @@</span><br><span> {</span><br><span>   u32 dword;</span><br><span>   void *usb2_bar0;</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t sm_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+      struct device *sm_dev;</span><br><span> </span><br><span>   sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));</span><br><span>       //rev = get_sb800_revision(sm_dev);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26405">change 26405</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26405"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie48b42cf2999df075e23dc8ba185934b4e600157 </div>
<div style="display:none"> Gerrit-Change-Number: 26405 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>