[coreboot-gerrit] Change in coreboot[master]: nvidia/mcp55: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sat May 19 10:56:00 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26400
Change subject: nvidia/mcp55: Get rid of device_t
......................................................................
nvidia/mcp55: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I48ab6d77be0201ac7b49b26e0366b6e3a1e5ac52
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/nvidia/mcp55/azalia.c
M src/southbridge/nvidia/mcp55/fadt.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/nvidia/mcp55/mcp55.c
M src/southbridge/nvidia/mcp55/mcp55.h
M src/southbridge/nvidia/mcp55/pci.c
M src/southbridge/nvidia/mcp55/smbus.c
7 files changed, 23 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/26400/1
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 2cb731c..c4b67cb 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -254,7 +254,7 @@
#endif
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c
index cade43d..8064b12 100644
--- a/src/southbridge/nvidia/mcp55/fadt.c
+++ b/src/southbridge/nvidia/mcp55/fadt.c
@@ -29,7 +29,7 @@
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- device_t dev;
+ struct device *dev;
int is_mcp55 = 0;
dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index ba9386b..b6bb1f8 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -53,7 +53,7 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-static void lpc_common_init(device_t dev, int master)
+static void lpc_common_init(struct device *dev, int master)
{
u8 byte;
void *ioapic_base;
@@ -70,7 +70,7 @@
clear_ioapic(ioapic_base);
}
-static void lpc_slave_init(device_t dev)
+static void lpc_slave_init(struct device *dev)
{
lpc_common_init(dev, 0);
}
@@ -84,7 +84,7 @@
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
}
-static void lpc_init(device_t dev)
+static void lpc_init(struct device *dev)
{
u8 byte, byte_old;
int on, nmi_option;
@@ -145,7 +145,7 @@
enable_hpet(dev);
}
-static void mcp55_lpc_read_resources(device_t dev)
+static void mcp55_lpc_read_resources(struct device *dev)
{
struct resource *res;
@@ -177,7 +177,7 @@
*
* @param dev The device whose children's resources are to be enabled.
*/
-static void mcp55_lpc_enable_childrens_resources(device_t dev)
+static void mcp55_lpc_enable_childrens_resources(struct device *dev)
{
u32 reg, reg_var[4];
int i, var_num = 0;
@@ -186,7 +186,7 @@
reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device *child;
for (child = link->children; child; child = child->sibling) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
@@ -234,14 +234,14 @@
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
}
-static void mcp55_lpc_enable_resources(device_t dev)
+static void mcp55_lpc_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
mcp55_lpc_enable_childrens_resources(dev);
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void southbridge_acpi_fill_ssdt_generator(device_t device)
+static void southbridge_acpi_fill_ssdt_generator(struct device *device)
{
amd_generate_powernow(0, 0, 0);
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c
index 7c43fea..4fe2a4e 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.c
+++ b/src/southbridge/nvidia/mcp55/mcp55.c
@@ -27,9 +27,9 @@
static u32 final_reg;
-static device_t find_lpc_dev(device_t dev, unsigned devfn)
+static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
{
- device_t lpc_dev;
+ struct device *lpc_dev;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
@@ -54,9 +54,9 @@
return lpc_dev;
}
-void mcp55_enable(device_t dev)
+void mcp55_enable(struct device *dev)
{
- device_t lpc_dev = 0, sm_dev = 0;
+ struct device *lpc_dev = 0, sm_dev = 0;
unsigned index = 0, index2 = 0;
u32 reg_old, reg;
u8 byte;
@@ -221,7 +221,7 @@
}
}
-static void mcp55_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void mcp55_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index a244b82..8d595c9 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -26,7 +26,7 @@
#ifndef __PRE_RAM__
#include "chip.h"
-void mcp55_enable(device_t dev);
+void mcp55_enable(struct device *dev);
extern struct pci_operations mcp55_pci_ops;
#else
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
diff --git a/src/southbridge/nvidia/mcp55/pci.c b/src/southbridge/nvidia/mcp55/pci.c
index 978fea4..bd92c7e 100644
--- a/src/southbridge/nvidia/mcp55/pci.c
+++ b/src/southbridge/nvidia/mcp55/pci.c
@@ -29,7 +29,7 @@
{
u32 dword;
u16 word;
- device_t pci_domain_dev;
+ struct device *pci_domain_dev;
struct resource *mem, *pref;
/* System error enable */
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index c41445b..244759d 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -27,7 +27,7 @@
#include "mcp55.h"
#include "smbus.h"
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device *dev)
{
unsigned device;
struct resource *res;
@@ -41,7 +41,7 @@
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device *dev, u8 val)
{
unsigned device;
struct resource *res;
@@ -55,7 +55,7 @@
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
unsigned device;
struct resource *res;
@@ -69,7 +69,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
unsigned device;
struct resource *res;
@@ -93,7 +93,7 @@
unsigned pm_base;
#endif
-static void mcp55_sm_read_resources(device_t dev)
+static void mcp55_sm_read_resources(struct device *dev)
{
unsigned long index;
@@ -106,7 +106,7 @@
compact_resources(dev);
}
-static void mcp55_sm_init(device_t dev)
+static void mcp55_sm_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
struct resource *res;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I48ab6d77be0201ac7b49b26e0366b6e3a1e5ac52
Gerrit-Change-Number: 26400
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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