[coreboot-gerrit] Change in coreboot[master]: nb/intel/nehalem: Fix smashed stack in romstage

[Matthias Gazzari (Code Review)]

Matthias Gazzari has uploaded this change for review. ( https://review.coreboot.org/26388


Change subject: nb/intel/nehalem: Fix smashed stack in romstage
......................................................................

nb/intel/nehalem: Fix smashed stack in romstage

Stack smashing was detected during raminit when not loading from MRC.
Adding CAR_GLOBAL to the ram timings variable solves the issue.

Tested on Lenovo X201i with 2+2 and 4+4 GB RAM.

Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1
Signed-off-by: Matthias Gazzari <mail at qtux.eu>
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 5 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/26388/1

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index df88ef3..6a27b57 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -44,6 +44,7 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <mrc_cache.h>
+#include <arch/early_variables.h>
 #endif
 
 #if !REAL
@@ -282,6 +283,9 @@
 	const struct ram_training *cached_training;
 };
 
+/* Global allocation of timings_car */
+timing_bounds_t timings_car[64] CAR_GLOBAL;
+
 static void
 write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
 	  int flag);
@@ -3128,7 +3132,7 @@
 	u8 reg_178;
 	int niter;
 
-	timing_bounds_t timings[64];
+	timing_bounds_t *timings = timings_car;
 	int lane, rank, slot, channel;
 	u8 reg178_center;
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1
Gerrit-Change-Number: 26388
Gerrit-PatchSet: 1
Gerrit-Owner: Matthias Gazzari <mail at qtux.eu>
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