[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/pch: Make infrastructure ready for pch common code

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26348


Change subject: soc/intel/common/pch: Make infrastructure ready for pch common code
......................................................................

soc/intel/common/pch: Make infrastructure ready for pch common code

This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).

All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.

A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.

BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option

Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/Kconfig
M src/soc/intel/common/Makefile.inc
A src/soc/intel/common/pch/Kconfig
A src/soc/intel/common/pch/Makefile.inc
4 files changed, 62 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26348/1

diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 6df62b6..3613965 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -8,6 +8,9 @@
 comment "Intel SoC Common Code"
 source "src/soc/intel/common/block/Kconfig"
 
+comment "Intel SoC Common PCH Code"
+source "src/soc/intel/common/pch/Kconfig"
+
 config DISPLAY_MTRRS
 	bool "MTRRs: Display the MTRR settings"
 	default n
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index bfd6a77..45865c1 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -2,6 +2,7 @@
 
 subdirs-y += basecode/
 subdirs-y += block/
+subdirs-y += pch/
 
 bootblock-y += util.c
 
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
new file mode 100644
index 0000000..6d8856c
--- /dev/null
+++ b/src/soc/intel/common/pch/Kconfig
@@ -0,0 +1,51 @@
+config SOC_INTEL_COMMON_PCH_BASE
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK
+	help
+	  Intel common PCH code based on Gen-6 Sunrisepoint PCH (SPT).
+	  All common PCH code blocks between Gen-6 till latest-PCH should be
+	  part of this directory. A SoC Kconfig might select this option to include
+	  base PCH package while building new SOC block. Currently majority of
+	  common IP code blocks are part of soc/intel/common/block/ and
+	  SoC Kconfig just select those Kconfig option. Now addition to that
+	  SoC might only selects required base PCH block to include those
+	  common IP block selections.
+
+if SOC_INTEL_COMMON_PCH_BASE
+
+comment "Intel SoC Common PCH Code"
+source "src/soc/intel/common/pch/*/Kconfig"
+
+config PCH_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
+	select SOC_INTEL_COMMON_BLOCK_CPU
+	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+	select SOC_INTEL_COMMON_BLOCK_CSE
+	select SOC_INTEL_COMMON_BLOCK_DSP
+	select SOC_INTEL_COMMON_BLOCK_EBDA
+	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	select SOC_INTEL_COMMON_BLOCK_GPIO
+	select SOC_INTEL_COMMON_BLOCK_GRAPHICS
+	select SOC_INTEL_COMMON_BLOCK_ITSS
+	select SOC_INTEL_COMMON_BLOCK_I2C
+	select SOC_INTEL_COMMON_BLOCK_LPC
+	select SOC_INTEL_COMMON_BLOCK_LPSS
+	select SOC_INTEL_COMMON_BLOCK_P2SB
+	select SOC_INTEL_COMMON_BLOCK_PCIE
+	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_PMC
+	select SOC_INTEL_COMMON_BLOCK_RTC
+	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_SATA
+	select SOC_INTEL_COMMON_BLOCK_SCS
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOC_INTEL_COMMON_BLOCK_SMM
+	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+	select SOC_INTEL_COMMON_BLOCK_SPI
+	select SOC_INTEL_COMMON_BLOCK_TIMER
+	select SOC_INTEL_COMMON_BLOCK_UART
+	select SOC_INTEL_COMMON_BLOCK_XDCI
+	select SOC_INTEL_COMMON_BLOCK_XHCI
+
+endif
diff --git a/src/soc/intel/common/pch/Makefile.inc b/src/soc/intel/common/pch/Makefile.inc
new file mode 100644
index 0000000..d6f53c8
--- /dev/null
+++ b/src/soc/intel/common/pch/Makefile.inc
@@ -0,0 +1,7 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK),y)
+
+subdirs-y += ./*
+
+CPPFLAGS_common += -I$(src)/soc/intel/common/block/include/
+
+endif

-- 
To view, visit https://review.coreboot.org/26348
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Gerrit-Change-Number: 26348
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180517/1d5b57fb/attachment-0001.html>