<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26348">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/pch: Make infrastructure ready for pch common code<br><br>This patch is intended to make Intel common PCH code based on<br>Gen-6 Sunrisepoint PCH (SPT).<br><br>All common PCH code blocks between Gen-6 till latest-PCH should be<br>part of soc/intel/common/pch/ directory.<br><br>A SoC Kconfig might select this option to include base PCH package<br>while building new SOC block. Currently majority of<br>common IP code blocks are part of soc/intel/common/block/ and<br>SoC Kconfig just select those Kconfig option. Now addition to that<br>SoC might only selects required base PCH block to include those<br>common IP block selections.<br><br>BUG=none<br>BRANCH=b:78109109<br>TEST=soc code can select PCH config option<br><br>Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/common/Kconfig<br>M src/soc/intel/common/Makefile.inc<br>A src/soc/intel/common/pch/Kconfig<br>A src/soc/intel/common/pch/Makefile.inc<br>4 files changed, 62 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26348/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig</span><br><span>index 6df62b6..3613965 100644</span><br><span>--- a/src/soc/intel/common/Kconfig</span><br><span>+++ b/src/soc/intel/common/Kconfig</span><br><span>@@ -8,6 +8,9 @@</span><br><span> comment "Intel SoC Common Code"</span><br><span> source "src/soc/intel/common/block/Kconfig"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+comment "Intel SoC Common PCH Code"</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/soc/intel/common/pch/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config DISPLAY_MTRRS</span><br><span> bool "MTRRs: Display the MTRR settings"</span><br><span> default n</span><br><span>diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc</span><br><span>index bfd6a77..45865c1 100644</span><br><span>--- a/src/soc/intel/common/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/Makefile.inc</span><br><span>@@ -2,6 +2,7 @@</span><br><span> </span><br><span> subdirs-y += basecode/</span><br><span> subdirs-y += block/</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += pch/</span><br><span> </span><br><span> bootblock-y += util.c</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..6d8856c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/pch/Kconfig</span><br><span>@@ -0,0 +1,51 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_PCH_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on SOC_INTEL_COMMON_BLOCK</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel common PCH code based on Gen-6 Sunrisepoint PCH (SPT).</span><br><span style="color: hsl(120, 100%, 40%);">+ All common PCH code blocks between Gen-6 till latest-PCH should be</span><br><span style="color: hsl(120, 100%, 40%);">+ part of this directory. A SoC Kconfig might select this option to include</span><br><span style="color: hsl(120, 100%, 40%);">+ base PCH package while building new SOC block. Currently majority of</span><br><span style="color: hsl(120, 100%, 40%);">+ common IP code blocks are part of soc/intel/common/block/ and</span><br><span style="color: hsl(120, 100%, 40%);">+ SoC Kconfig just select those Kconfig option. Now addition to that</span><br><span style="color: hsl(120, 100%, 40%);">+ SoC might only selects required base PCH block to include those</span><br><span style="color: hsl(120, 100%, 40%);">+ common IP block selections.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+if SOC_INTEL_COMMON_PCH_BASE</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+comment "Intel SoC Common PCH Code"</span><br><span style="color: hsl(120, 100%, 40%);">+source "src/soc/intel/common/pch/*/Kconfig"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config PCH_SPECIFIC_OPTIONS</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CSE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_DSP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_EBDA</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GRAPHICS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_I2C</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_LPSS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PCIE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PCR</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_PMC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_RTC</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SA</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SCS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SMBUS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SMM</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_UART</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_XHCI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/soc/intel/common/pch/Makefile.inc b/src/soc/intel/common/pch/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..d6f53c8</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/pch/Makefile.inc</span><br><span>@@ -0,0 +1,7 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK),y)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+subdirs-y += ./*</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+CPPFLAGS_common += -I$(src)/soc/intel/common/block/include/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26348">change 26348</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b </div>
<div style="display:none"> Gerrit-Change-Number: 26348 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>